Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-03
2002-05-28
Fahmy, Wael (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000, C257S402000, C438S290000, C438S291000
Reexamination Certificate
active
06396103
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to semiconductor devices such as field effect transistors.
BACKGROUND OF THE INVENTION
In a field effect transistor, leakage current is a critical parameter. Leakage current is the drain current, I
Doff
, which flows when the drain is biased normally and the gate to source voltage is set to zero volts. In very large scale integrated circuits employing hundreds of thousands of transistors, the aggregate leakage current can substantially increase overall power dissipation. Hence, there is a need to minimize leakage current for each individual transistor.
In an individual transistor, the leakage current has two components. A first component is surface leakage, which occurs in the channel between the source diffusion and the drain diffusion near the surface of the semiconductor, at the semiconductor-oxide interface. A second component is located deeper in the channel, more distant from the surface, between the source and drain. Control of leakage current requires control of both components.
Previous attempts to control and limit field effect transistor leakage current have involved implantation of doping ions in the channel, under the gate of the transistor, to provide a laterally uniform doped channel. Prior to gate formation, a window is opened in an oxide layer at the location of the channel. Using standard semiconductor processing techniques, an ion implant is made to shift the threshold voltage of the transistor and to limit the leakage current. This ion implantation step results in substantially uniform doping along the length of the channel (from source to drain).
However, this type of leakage current control requires a tradeoff between the leakage current, I
Doff
, and the saturation drain current, I
Dsat
, when the transistor is fully turned on. For best transistor performance (i.e., maximum drain current and switching speed), I
Dsat
should be maximized. However, the uniform ion implant used to minimize the leakage current tends to reduce I
Dsat
.
Accordingly, there is a need in the art for a method and apparatus providing reduced transistor leakage current without affecting saturation drain current.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a field effect transistor including a semiconductor substrate, a source region and a drain region formed in the semiconductor substrate, and a gate stack formed on a surface of the semiconductor substrate adjacent to the source region and the drain region. The gate stack defines a channel region in the semiconductor substrate. The field effect transistor further includes a source side halo region formed at a junction between the source region and the channel region to a substantially interrupt off-state leakage current in the field effect transistor.
The invention further provides a method for manufacturing a field effect transistor. The method includes steps of forming a source region and a drain region in a semiconductor substrate, forming a gate stack on a surface of the semiconductor substrate to define a channel region in the semiconductor substrate between the source region and the drain region, and implanting doping ions in the channel region proximate the source to a depth sufficient to substantially interrupt both surface and deep channel leakage current and asymmetrically dope the channel region.
The present invention further provides a method for manufacturing a field effect transistor including steps of forming a source region and a drain region in a semiconductor substrate, forming a gate stack on a surface of the semiconductor substrate and forming a source extension along a gate side of the source region. The source extension has an extension depth less than depth of the source region. The method further includes implanting doping ions at a source side of the channel, including steps of implanting first doping ions at a first angle and a first energy to locate the first doping ions near the surface at the source side of the channel, and implanting second doping ions at a second angle and second energy to locate the second doping ions near the extension depths at the source side of the channel.
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Hiroki et al., A High Performance 0.1 &mgr;m MOSFET with Asymmetric Channel Profile; International Electron Devices Meeting 1995, pp. 439-442.
S. M. Sze,Physics of Semiconductor Devices,Second Edition, published by John Wiley & Sons, pp. 489-490.
Odanaka et al., Potential Design and Transport Property of 0.1 &mgr;m MOSFET with Asymmetric Channel Profile; IEEE Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, pp. 595-600.
Ohzone et al., Influence of Asymmetric/Symmetric source/Drain Region on Asymmetry and Mismatch of CMOSFET's and Circuit Performance; IEEE Transactions on Electron Devices, vol. 45, No. 2, Feb. 1998, pp. 529-537.
Huster Carl Robert
Riccobene Concetta
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Fahmy Wael
Garcia Joannie A.
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