Optimized metal stack strategy

Details Optimized metal stack strategy Optimized metal stack strategy

2001-08-28

2003-07-01

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06587991

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to ASIC design and implementation, and more particularly to a metal stack strategy for ASICS.
BACKGROUND OF THE INVENTION
Metal interconnects connect gates and other devices in electronic circuitry, and are having an increasing large role in ASICS (Application Specific Integrated Circuit) in terms of performance and manufacturing. In deep sub-micron ASIC design, for instance, interconnects are overtaking the transistor as being the dominant factor affecting performance. That is, full performance of an ASIC design cannot be realized if the metal interconnects comprising the circuits are not optimized.
FIG. 1
is a block diagram illustrating the physical properties of interconnects
10
that can affect performance. When patterned on a substrate, each interconnect
10
is patterned with a certain width
12
and thickness (depth)
14
. The spacing between adjacent interconnects
10
is called pitch
16
, which is measured between the centerlines of interconnects
10
.
With older process technology, the various layers of metal comprising the interconnects
10
could only be patterned relatively thick, which meant that they had to also be patterned very wide. This was disadvantageous because if the interconnects
10
could have been patterned thinner, a smaller width
12
could have been used, thereby saving space. Therefore, older process technology afforded designers little freedom in that the designers had no choice but to pattern the interconnects
10
fairly wide. As far as performance is concerned, wider interconnects
10
may reduce resistance, but the trade-off is that wide interconnects
10
waste space and do not result in very compact circuits.
Current process technology is capable of producing much thinner interconnects
10
than older process technology, and today designers attempt to pattern the interconnects
10
with the smallest possible geometry (width and thickness). One problem with patterning the interconnects
10
using the smallest possible geometry is that if the metal is patterned too thin widthwise, the interconnects
10
may have high resistance, which could throw off circuit timing and reduce performance. The benefit, however, of thin interconnects
10
is that higher compactness is achieved, posing designers with a potential trade-off between performance and compaction.
If the interconnects
10
are automatically patterned with the smallest possible geometry, the only variable left to designers to optimize performance of the interconnects
10
is to widen the pitch
16
. Defining a metal stack strategy based on manufacturable wire sizes rather than on design requirements produces unacceptable results because minimum manufacturable wire sizes fail to deliver results in terms of performance and compaction.
Interconnects are also playing an important role in ASIC manufacturing. Custom ASICs are typically fabricated from ASIC cores. Once a custom ASIC is designed, a finished ASIC core is taken off the shelf and customized by placing metal stacks on top of the ASIC core to complete the custom design. Basically, a metal stack option in an ASIC core includes up to four metal interconnect layers (in the 0.18 &mgr;m and 0.13 &mgr;m node technologies). Four or more additional interconnect layers may then be added to the ASIC core to fabricate the custom ASIC with a total of eight or more metal interconnect layers.
A manufacturer may have many different metal stack options available. However, not all metal stack options will accept every ASIC core. In most current process technology, this requires most manufacturers to design each ASIC core multiple times, one for every metal stack option available. That is, every time a manufacturer uses a new process technology to create a new metal stack, a new core must be designed and created that is compatible with the new metal stack. Process technology changes every 15-18 months, but it may take up to six months to create a new core. Obviously, designing a new core for every metal tack option is expensive and time-consuming.
What is needed is an improved metal stack strategy. The metal stack strategy should optimize metal stack performance and eliminate the need to design an ASIC core for every metal stack option offered. The present invention addresses such needs.


REFERENCES:
patent: 6018623 (2000-01-01), Chang et al.
patent: 6265746 (2001-07-01), Madurawe et al.
patent: 6327394 (2001-12-01), Kash et al.
patent: 6381730 (2002-04-01), Chang et al.
patent: 6516456 (2003-02-01), Garnett et al.

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