Optimized memory addressing

Details Optimized memory addressing Optimized memory addressing

2007-06-12

2007-06-12

Tung, Kee M. (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Plural storage devices

C345S531000, C345S536000, C345S537000

Reexamination Certificate

active

10796686

ABSTRACT:
Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

REFERENCES:
patent: 6469703 (2002-10-01), Aleksic et al.

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