Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-01
2001-09-25
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C438S631000, C438S759000, C438S763000
Reexamination Certificate
active
06294457
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of improving yield in a damascene method in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying conductive area to which electrical contact is to be made. A conducting layer material is deposited within the contact/via opening. The damascene and dual damascene processes have become a future trend in metallization. Trenches or vias and trenches are etched in an insulating layer. The trenches or vias and trenches are inlaid with metal to complete the contacts. It is desired to use low dielectric constant (low-k) materials in order to reduce capacitance of the resulting devices. Silicon carbide (SiC) or silicon nitride (SiN) is widely used to improve adhesion when using organic low-k materials in the intermetal dielectric layers (IMD). To avoid micro-scratching during the final polishing metal step, a minimal amount of the low-k material should be polished. To accomplish this, a polish stop layer is provided over the low-k material. The use of SiC, SiN, or silicon oxynitride (SiON) as the polish stop layer will cause a problem at the pre-metal deposition step. After the trench has been etched through the IMD layer, an Ar sputtering cleaning step is performed. The polish stop layer, which is the topmost layer of the IMD layer, will be exposed to the Ar sputtering. The sputtering chamber walls are typically composed of quartz (SiO
2
). Adhesion between the SiON and quartz is poor, resulting in peeling of the SiON on the chamber walls due to thermal stress from wafer to wafer processing. Particles generated from this peeling will undesirably contaminate the wafer. It is desired to find a IMD scheme that will avoid the particle issue and hence lead to yield improvement.
U.S. Pat. No. 6,100,181 to You et al discloses a dual damascene process. U.S. Pat. No. 6,083,850 to Shields uses HSQ, a low-k material, as a gap-filling layer. U.S. Pat. Nos. 5,891,799 to Tsui and 5,858,870 to Zheng et al teach non-damascene IMD schemes. U.S. Pat. No. 6,071,809 to Zhao shows a dual damascene process using a silicon nitride polish stop layer with an overlying protection layer. Preferably, the protection layer is silicon dioxide, but it may also be silicon oxynitride or other materials that will cause particle problems.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of metallization in the fabrication of integrated circuit devices.
Another object of the invention is to provide a method of metallization while avoiding particle issues during pre-metal cleaning.
A further object of the invention is to provide a method of metallization wherein particle issues are avoided during pre-metal cleaning by the use of a unique IMD scheme.
Yet another object of the invention is to provide a method of metallization wherein particle issues are avoided during pre-metal cleaning by the use of a unique IMD scheme including a silicon oxide layer overlying the polish stop layer.
In accordance with the objects of this invention a new method of metallization wherein particle issues are avoided during pre-metal cleaning by the use of a unique IMD scheme is achieved. A semiconductor substrate is provided which may include semiconductor device structures. An etch stop layer is deposited overlying the semiconductor substrate. A low-dielectric constant material layer is deposited overlying the etch stop layer. A polish stop layer is deposited overlying the low-dielectric constant material layer. An oxide layer is deposited overlying the polish stop layer. An anti-reflective coating (ARC) layer is deposited overlying the oxide layer. An opening is etched through the ARC layer, oxide layer, polish stop layer, and low-dielectric constant material layer where they are not covered by a mask. The mask is removed during etching. The etch stop layer is etched through within the opening whereby the ARC layer is removed. The opening is cleaned using an Argon sputtering method. Since the topmost layer of the IMD layer is an oxide layer, particles are not generated from this topmost layer. The opening is filled with a metal layer to complete metallization in the fabrication of an integrated circuit device.
REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 5858870 (1999-01-01), Zheng et al.
patent: 5891799 (1999-04-01), Tsui
patent: 6004188 (1999-12-01), Roy
patent: 6011809 (2000-01-01), Tosaka
patent: 6025277 (2000-02-01), Chen et al.
patent: 6071809 (2000-06-01), Zhao
patent: 6080529 (2000-06-01), Ye et al.
patent: 6083850 (2000-07-01), Shields
patent: 6100181 (2000-08-01), You et al.
patent: 6143646 (2000-11-01), Wetzel
patent: 6165695 (2000-12-01), Yang et al.
patent: 6180512 (2001-01-01), Dai
patent: 6242344 (2001-06-01), Koh et al.
Ackerman Stephen B.
Lebentritt Michael
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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