Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-07-22
2004-03-16
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S300000, C710S260000, C710S107000, C710S052000, C710S021000, C710S027000, C710S029000, C710S035000
Reexamination Certificate
active
06708244
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to interface devices generally and, more particularly, to an interface device in an intelligent input/output system.
BACKGROUND OF THE INVENTION
An intelligent input/output system is defined by the Intelligent I/O (I
2
O) Architecture Specification, version 1.5, dated March 1997, and the Intelligent I/O (I
2
O) Architecture Specification, version 2.0, dated March 1999, the relevant portions of each which are hereby incorporated by reference.
FIG. 1
shows a circuit
10
implementing such an architecture. The circuit
10
is shown having a messaging unit (including four FIFO control logic blocks
12
,
14
,
16
and
18
), a shared memory
20
to store message frames, an interrupt block
22
, a first system interface bus
24
, a local bus interface bus
26
and a local processor
28
. The structure of the circuit
10
is described in the I
2
O Architecture Specification on pages 4-2 through 4-7. The circuit
10
illustrates the typical structure of an I
2
O messaging unit. In current solutions, the logic is distributed among up to three distinct elements connecting two buses of two different clock domains. The three elements are a processing component, a random access memory component, and a bus interface component. The circuit
10
suffers from several problems including (i) increased design complexity, (ii) increased manufacturing complexity, and (iii) decreased overall performance.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.
The objects, features and advantages of the present invention include providing a messaging unit that may be used in an I
2
O system that may (i) optimize messaging functions, (ii) minimize circuit card complexity, (iii) increase performance of the I
2
O message passing protocol, (iv) minimize component and manufacturing costs, (v) allow simultaneous access to the messaging unit by two buses, (vi) allow simultaneous access to a message frames storage device and the message queue storage device, (vii) place the message unit storage device in a central arbitrated area having a single clock domain, (viii) allow operation of a first and second bus having an independent clock domain, and/or (ix) implement the messaging unit as a self contained, single chip solution implementing all hardware required for an I
2
O compliant messaging unit.
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Intelligent I/O (I2O) Architecture Specification, Version 1.5, Mar. 1997, pp. 4-1 through 4-71.
Intelligent I/O (I2O) Architecture Specification, Version 2.0, Mar. 1999, pp. 4-1 through 4-96.
CO-MEM Lite, AN3042 Integrated Circuit Preliminary Data Sheet, Anchor Chips Incorporated, Version 0.9, Jul. 7, 1998, pp. 1-47.
Black B. David
Clark Leah S.
Larky Steven P.
Podsiadlo David A.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Shin Christopher B.
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