Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-07-11
2008-08-05
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S147000
Reexamination Certificate
active
07409505
ABSTRACT:
A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). A directory cache is held in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.
REFERENCES:
patent: 5265232 (1993-11-01), Gannon et al.
patent: 5634110 (1997-05-01), Laudon et al.
patent: 5680576 (1997-10-01), Laudon
patent: 5752258 (1998-05-01), Guzovskiy et al.
patent: 5778437 (1998-07-01), Baylor et al.
patent: 5787477 (1998-07-01), Rechtschaffen et al.
patent: 5900015 (1999-05-01), Herger et al.
patent: 5937431 (1999-08-01), Kong et al.
patent: 6631447 (2003-10-01), Morioka et al.
patent: 6651145 (2003-11-01), Jamil et al.
patent: 6748498 (2004-06-01), Gharachorloo et al.
patent: 6925547 (2005-08-01), Scott et al.
patent: 7103726 (2006-09-01), Glasco
Lenoski, D., et al., “The Stanford Dash Multiprocessor”, Computer, 25, (Mar. 1992), pp. 63-79.
Chaiken, D. , et al., “LimitLESS Directories: A Scalable Cache Coherence Scheme”,Proceedings: Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA,(Apr. 8-11, 1991),224-234.
Laudon, J. , et al., “The SGI Origin: A ccNUMA Highly Scalable Server”,Computer ARchitecture News, vol. 25, No. 2, XP000656582, (May 1997),241-251.
Lenoski, D. , et al., “The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor”,Proceedings: The 17th Annual International Symposium on Computer Architecture, Seattle, Washington,(May 28-31),148-159.
Lenoski, D. , et al., “The Stanford Dash Multiprocessor”,Computer, 25, (Mar. 1992),63-79.
Morris, John , “Computer Architecture: The Anatomy of Modern Processors”,Internet Website: Http://ciips.ee.uwa.edu.au/˜morris/CA406/cache—coh.html on Apr. 29, 2002, (1998),6 pgs.
Papamarcos, M. S., et al., “A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories”,Proceedings: The 11th Annual International Symposium on Computer Architecture, Ann Arbor, Michigan—(*Lines (Underlined Words) in Publication are supposed to be there),(Jun. 5-7, 1984),348-354.
Scott, Steve L., et al., “Performance of Pruning-Cache Directories for Large-Scale Multiprocessors”,IEEE Transactions on Parallel and Disbributed Systems, vol. 4, No. 5,(1993),pp. 520-534.
Bataineh Abdulla
Scott Steven L.
Cray Inc.
Nguyen T
Schwegman Lundberg & Woessner, P.A.
LandOfFree
Optimized high bandwidth cache coherence mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimized high bandwidth cache coherence mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized high bandwidth cache coherence mechanism will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3997972