Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-11
2004-11-23
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S346000, C257S351000
Reexamination Certificate
active
06822291
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the gate etching process used during integrated circuit fabrication. More specifically, the present invention pertains to a method to make the gate etching endpoint signal stronger and more consistent.
BACKGROUND ART
Integrated circuits are fabricated en masse on silicon wafers using well-known techniques such as photolithography. Using these techniques, a pattern (“mask”) that defines the size and shape of the components and gates within a given layer of the die is applied to the wafer. The pattern applied to the wafer is laid out in an array, or matrix, of reticle images. A wafer stepper holds the pattern over a wafer and projects the pattern image of the reticle onto the wafer.
Prior Art
FIG. 1A
shows a laminate
10
used in the fabrication of integrated circuits in accordance with one typical prior art embodiment. Laminate
10
includes a substrate
15
(e.g., a silicon-based semiconductor), a gate dielectric layer
16
(e.g., silicon dioxide or some other dielectric material), and a gate electrode layer
17
(e.g., n-doped polysilicon).
With reference next to Prior Art
FIG. 1B
, in order to form gate
20
, portions of gate electrode layer
17
are removed, typically using a gate etch process. As described above, a photolithography process is used in a known manner to apply a gate mask
22
at the location at which gate
20
will be formed. When an etchant (e.g., a plasma etch) is then applied, the portions of gate electrode layer
17
around gate
20
are removed, while the material under gate mask
22
remains to form the gate (see Prior Art FIG.
1
C).
Traditionally, integrated circuits were made with n-type polysilicon gates. The polysilicon was doped n-type during polysilicon deposition by adding PH
3
or after polysilicon deposition using POCl
3
. Thus, the gate etch process had to remove only n-type polysilicon in order to form the gates.
For deep submicron CMOS (complementary metal-oxide semiconductor) circuits, dual-implanted polysilicon or amorphous silicon is preferred (for simplicity in the discussion, both will be referred to as “polysilicon” or “poly”). After depositing undoped poly, implant masks are used to create n-type poly over n-channel transistors and p-type poly over p-channel transistors. Depending on the implant mask arrangement, some portions of the poly may not be doped at all (“undoped” or “unimplanted”), and other portions may be doped with both types of dopant material (n/p-doped). Such dual-implanted polysilicon allows for better control of the p-channel transistor properties.
However, the dual-implanted poly can create a problem during the gate etch process, because some combination of undoped, n-doped, p-doped, and n/p-doped poly will be exposed to the etchant. Each of these differently doped polysilicons will etch at a different rate. In general, p-doping will depress the etch rate, while n-doping will enhance it. The difference in etch rates can be significant; for example, when HBr/O
2
etchant is used, the difference in the etching rate between p-doped poly and n-doped poly can be as much as 37 percent. Such large differences in etch rates increase the likelihood of microtrenching of the gate oxide layer; that is, a local breakthrough of the gate oxide layer followed by etching into the silicon layer adjacent to the gate oxide layer. Microtrenching is not desirable because it introduces a variable into the fabrication process and may also affect the electrical properties of the integrated circuit.
Prior Art
FIG. 2A
shows a laminate
30
used in the fabrication of integrated circuits (e.g., a CMOS) in accordance with one typical prior art embodiment. Laminate
30
includes a substrate
35
, typically a silicon-based semiconductor layer; a gate dielectric layer
36
, typically silicon dioxide or some other dielectric material; and gate electrode layer
37
, typically doped polysilicon. Here, a p-gate
41
and an n-gate
42
are to be formed in the particular locations shown. Accordingly, gate electrode layer
37
includes a p-doped region
43
encompassing the location of p-gate
41
and an n-doped region
44
encompassing the location of n-gate
42
.
In the prior art, the p-dopant material and the n-dopant material are implanted in a known manner using implant masks. These implant masks are used to broadly implant the correct dopant material in the proper locations (e.g., p-doped region
43
and n-doped region
44
). P-gate
41
and n-gate
42
are then formed by removing the excess portions of gate electrode layer
37
using a gate etch process. Since the excess portions are removed to form the gate, in general it is important only that the doped regions bound the locations where the gates will be formed.
With reference now to Prior Art
FIG. 2B
, p-doped region
43
will etch away at a slower rate than n-doped region
44
. As a result, when n-doped region
44
has been removed by etching, forming n-gate
42
, portions of the p-doped region (p-doped regions
43
a
and
43
b
) will still remain. Should the gate etch process continue in order to remove p-doped regions
43
a
and
43
b
, the etchant can form microtrenches (e.g., microtrench
50
) in gate dielectric layer
36
.
To avoid microtrenching while retaining the benefits of dual-implanted poly in CMOS design, it is important to signal endpoint when n-doped region
44
is cleared. At endpoint, the gate etch process is halted, and a different etchant is introduced. The new etchant exhibits greater selectivity between p-doped regions
43
a
and
43
b
and gate dielectric layer
35
; that is, the new etchant will work to clear p-doped regions
43
a
and
43
b
without operating on gate dielectric layer
35
, so that microtrenches will not be formed.
However, a problem in the prior art is that the endpoint signal may be too weak to detect; therefore, it does not trigger endpoint and the switch to the different etchant. In those cases, the gate etch process continues for too long using the nonselective etchant, and microtrenching is thus likely to occur.
Accordingly, what is needed is a method and/or apparatus that can improve the endpoint signal, so that endpoint is consistently triggered at the correct moment and microtrenching is prevented. What is also needed is a method and/or apparatus that can address the above need and that can be used with laminates using various combinations of undoped, n-doped, p-doped, and n/p-doped polysilicon with significantly different etch rates. The present invention provides a novel solution to the above needs.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
DISCLOSURE OF THE INVENTION
The present invention provides a method and apparatus thereof that can improve the endpoint signal, so that endpoint is consistently triggered at the correct moment and microtrenching is prevented. The present invention can also be used with laminates using various combinations of undoped, n-doped, p-doped, and n/p-doped polysilicon with significantly different etch rates.
In accordance with the present embodiment of the present invention, detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material and minimizing the use of a slower etching dopant material in the gate electrode layer. The faster etching dopant material will etch away faster, and because the gate electrode layer is predominantly made up of the faster etching dopant material, a strong and detectable endpoint signal will be induced when the etchant reaches the silicon dioxide layer.
In one embodiment, a first portion of the gate electrode layer, substantially corresponding only to the location at which a gate is to be formed, is doped with the slower etching dopant material. A second portion of the gate electrode layer, larger than the first portion, is doped with the faster etching dopant materi
de Muizon Emmanuel
Gabriel Calvin Todd
Leard Linda A.
Zheng Tammy D.
Dickey Thomas L.
Koninklijke Philips Electronics , N.V.
Zawilski Peter
LandOfFree
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