Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-12-12
2006-12-12
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000, C365S201000
Reexamination Certificate
active
07149941
ABSTRACT:
A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the register to fix both multi-cell fails and single-cell fails. A second fault correction system does not access said register and fixes single-cell fails. During testing, if a multi-cell fail is detected the register stores its address by deleting an address of a single-cell fail if the register is full.
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Adams R. Dean
Salem Gerard M.
von Reyn Timothy J.
De'cady Albert
Gandhi Dipakkumar
International Business Machines - Corporation
LeStrange Michael J.
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