Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1997-04-09
1998-12-29
Niebling, John
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438723, 438301, 438305, 438307, 438 16, H01L 21302, H01L 21461
Patent
active
058541357
ABSTRACT:
An anisotropic RIE procedure for creating a small diameter SAC opening, in an insulator layer, used in the fabrication sequence of a MOSFET device, and using a large area test site for RIE end point monitoring, has been developed. The RIE procedure features a RIE ambient, including oxygen as part of the RIE ambient, resulting in equal amounts of polymer deposition on the small diameter SAC opening, as well as on the large area test sites, during the reactive ion etching of the small diameter, SAC opening. This allows accurate monitoring of the RIE procedure to be performed on the large area test site, using optical ellipsometry procedures.
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Ackerman Stephen B.
Niebling John
Saile George O.
Vanguard International Semiconductor Corporation
Zarneke David A.
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