Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-06-30
2002-08-13
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S143000, C711S151000
Reexamination Certificate
active
06434673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for optimizing cache service requests.
2. Background Information
Caches are memory storage devices, and a microprocessor may have multiple cache levels. The cache situated closest to the processor typically has the smallest size and fastest access time. The cache situated farthest from the processor typically has a larger size and slower access time than a cache situated closest to the processor. The caches situated farthest from the processor typically take up significant die size. Also, the size of a cache is dependent upon, among other things, the access time, power, die size, etc.
Depending upon the addressing scheme and cache architecture, different addresses can map to the same set in a cache. As the size of the cache becomes smaller, the number of addresses mapped into a single set increase. Upon an incoming data request, a tag comparison is done to determine whether the request is a hit or miss. The status of the line is also checked to determine if the data in the cache is valid. A cache miss indicates that the data in the cache is from a different address, or it is not valid. When new data is written into the cache from the processor core, the status of the line is updated to a modified state.
On a cache miss to a given cache address, the data can be fetched and replaced into the cache either from main memory or a higher level cache. Before this new data is replaced into the cache, however, any modified data that already exists in the cache needs to be written back to main memory or to a cache further away from the processor core. These writebacks are also known as “dirty victims.” They are the consequence of cache misses to a set with previously modified data. These writebacks to main memory slow down incoming cacheable requests to the same set, as the latter need to wait for the cache eviction to occur before they can complete the replace into the cache.
The number of writebacks occurring in a given period of time is typically a function of the cache size, architectural implementation of the cache and number of cache misses. Typical cache controllers allocate a queue with certain number of request entries that are exclusively used to service cache writebacks. A separate queue or set of buffers also exist to exclusively service incoming core cacheable and uncacheable requests, as shown in FIG.
1
. While the scheme of allocating a preset number of entries for exclusive servicing of writebacks is easy to implement, this scheme may leave entries unused for long periods of time when there are no evictions. Therefore, the die size allocated to hardware resources will not be fully used.
Typical cache controllers have separate request entries to service writebacks and incoming core requests. Even with a cache controller designed to only have a single queue, as illustrated in
FIG. 2
, a fixed predetermined number of the controller's request entries are allocated exclusively to service writeback evictions. Since both writeback request entries and core request entries store data and addresses, the die size area for each of these entries is similar. A given entry can therefore service either a writeback eviction or a core request without any die size impact.
Consider an integrated microprocessor system in which the cache farthest from the processor is shared with CPU (central processing unit) and graphics data. The cache may exist in either a shared mode, where the cache contains both CPU and graphics data, or a CPU only mode, where the cache contains only CPU data. The cache mode is typically programmable and the shared portion of the cache is flushed upon a context switch, i.e., when the mode changes from shared to CPU only mode. During a context switch, multiple back-to-back writebacks occur, while no incoming core requests are accepted. In a system with separate queues, only the writeback entries are used during a context switch. Therefore, the entries allocated for servicing core requests are idle. This results in a loss of bandwidth to and from the cache.
REFERENCES:
patent: 5581729 (1996-12-01), Nishtala et al.
patent: 5634068 (1997-05-01), Nishtala et al.
patent: 5655100 (1997-08-01), Ebrahim et al.
patent: 5657472 (1997-08-01), Loo et al.
patent: 5684977 (1997-11-01), Loo et al.
patent: 5905998 (1999-05-01), Ebrahim et al.
patent: 6038645 (2000-03-01), Nanda et al.
patent: 6266743 (2001-07-01), Carpenter et al.
Mosur Lokpraveen B.
Palanca Salvador
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Thai Tuan V.
LandOfFree
Optimized configurable scheme for demand based resource... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimized configurable scheme for demand based resource..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized configurable scheme for demand based resource... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2962451