Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-06-27
2006-06-27
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S158000, C345S535000, C345S582000
Reexamination Certificate
active
07069387
ABSTRACT:
A method for optimizing a cache memory used for multitexturing in a graphics system is implemented. The graphics system comprises a texture memory, which stores texture data comprised in texture maps, coupled to a texture cache memory. Active texture maps for an individual primitive, for example a triangle, are identified, and the texture cache memory is divided into partitions. In one embodiment, the number of texture cache memory partitions equals the number of active texture maps. Each texture cache memory partition corresponds to a respective single active texture map, and is operated as a direct mapped cache for its corresponding respective single active texture map. In one embodiment, each texture cache memory partition is further operated as an associative cache for the texture data comprised in the partition's corresponding respective single active texture map. The cache memory is dynamically re-configured for each primitive.
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m38316420at0 512 mb ddr sdram modlue data sheet, Samsung Apr. 2000.
Doan Duc T
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Padmanabhan Mano
Sun Microsystems Inc.
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