Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1997-06-02
2001-03-20
Beausoliel, Jr., Robert W. (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06205564
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an optimized built-in self-test method and apparatus for detecting a predetermined set of faults in memory modules.
BACKGROUND OF THE INVENTION
This invention relates to an optimized built-in self-test method and apparatus for detecting faults in memory circuits to ensure an acceptable quality level of the RAMs and, more particularly, to detecting one or more of stuck-open faults, retention faults or state coupling faults using both technology independent and dependent test methods and apparatus.
Computers generally consist of three subsystems: the CPU, input/output devices, and memory subsystems. Memory subsystems include static memory, e.g.,a hard drive, in which data or programs are stored for long term retrieval, and active memory, in which the results of program execution are temporarily stored. Active memory is usually made up of semiconductor memory chips such as Random Access Memory (RAM) chips. RAMs hold large quantities of data bits and afford short access time. However, such advantages necessitate a high cost per bit held in the RAM memory array. In addition, since memory chips are used in large quantities in digital systems, memory chip faults are a prime contributor to failure rates in such systems.
Ongoing developments for increasing the density of RAMs have resulted in an increased likelihood of faults. Historically, the number of bits per chip has quadrupled roughly every 3.1 (or &pgr;) years. This exponential increase in density means that the area per memory cell is decreasing exponentially. As a consequence, the charge stored in the capacitor of a RAM cell is decreasing rapidly, causing the cell to be more susceptible to disturbances due to use (noise, crosstalk, etc.) and in the manufacturing process (differences in the capacitance or leakage current).
Also, due to increased density, RAM cells are placed closer together, which makes them more sensitive to influences from neighboring cells, which increases the likelihood of disturbances due to noise on address and data lines. The influence of neighboring cells can also result in “linking faults,” namely a fault occurring in one cell which causes a fault to occur in an otherwise properly functioning cell (referred to as a linked cell).
Accordingly, the quantity of faults and the likelihood of multiple, rather than single, faults occurring at a given time is increasing. Also, the types of faults which occur are increasing in complexity (e.g., linked faults).
At the same time, success in the memory industry is directly tied to controlling the production costs for RAMs, since fierce competition has driven down prices. The raw materials and fabrication steps for a RAM are relatively inexpensive, so the testing cost is the most significant production cost. The testing cost is primarily determined by the time required to test a given RAM. However, opposing the requirement for short testing times is the requirement that the tests be long enough to detect the various types of faults that are likely to occur. Accordingly, optimizing the testing time is constrained by the requirement that the test detect a given number of faults which ensure an acceptable quality level for RAMs.
Since effective memory testing lies on the critical path for preventing failures in digital systems and driving the industry, detection of increasingly complex faults must be accomplished using optimized tests. The process of designing an algorithm to accomplish this goal consists of the following: first, since testing for all possible faults is not feasible, the faults necessary to detect in order to ensure an acceptable quality level for a memory circuits, e.g., RAMs, are identified; and, second, the algorithm necessary to detect each individual fault is determined and combined into a single optimized algorithm for detecting the set of predetermined faults.
First, the basis for establishing a quality level acceptable for memory units is formulated by creating a fault model or precise descriptions of analog or digital defects that violate the memory's specifications. The resulting fault model will contain a set of predetermined faults to be detected in the memory. Fault modeling is an essential first step to the design of an optimized test. Many fault models for addressing single and multiple, and linked and unlinked, faults in memory circuits, e.g., RAMs, have been proposed in the art. In addition, individual faults included in such fault models are well known in the art.
Examples of traditional fault models are set forth in U.S. Pat. No. 5,513,318, issued on Apr. 30, 1996 and filed on Dec. 28, 1994, to A. J. van de Goor and Yervant Zorian and in the publications provided in the references cited section of such patent. In addition, traditional fault models are also provided in the article “
RAM Testing Algorithms For Detection Multiple Linked Faults
”, by V. G. Mikitjuk, V. N. Yarmolik, A. J. van de Goor,
IEEE
1996
European Design
&
Test Conference
, pp. 435-439, Mar. 1996; in Table 4, fault types are provided in the column labeled DETECTED FAULTS. Subsets of the detected faults are applicable to the tests listed in the TEST column. For example, for the test MATS+, the fault model contains two faults, an Address Decoder Fault and a Stuck-At Fault. For the March A test, the fault model consists of the MATS+ test faults as well as a Transition Fault, an Inversion Coupling Fault, an Indempotent Fault and Linked Indempotent Faults.
However, there are additional faults which may be detected to ensure an acceptable quality level for RAMs. While the additional faults individually may be known, the combination of two or more particular faults to create an optimized fault model which ensures an acceptable quality level may be heretofore unknown. Therefore, there is a need to identify particular faults which must be included in a fault model in order to ensure an acceptable quality level for RAMs under test.
Second, with a given fault model, the algorithm necessary to detect each fault within the model is determined. The set of individual algorithms, each of which is applicable to a particular fault, is then combined and reduced based on a computational model to a single algorithm. The single algorithm is then optimized to use the smallest number of operations necessary to detect all faults in the given model. The purpose of optimizing the operations in the algorithm to the smallest number is to accelerate the testing time.
Currently, a family of algorithms, called March tests or March algorithms, are well known and have proven superior to other tests because of the simplicity of the algorithms and the resulting optimization of the testing times. A March test consists of a sequence of March elements. A March element is a finite sequence comprising one or more read/write operations applied to a cell in memory before proceeding to the next cell, so that every cell in the memory is completely tested in sequence.
Another well known mechanism with which to optimize the testing time is the inclusion of circuitry in a memory circuit which allows the chip to perform testing autonomously. This technique is well known in the art as “built-in self-test” or BIST. BIST allows the hardware of the memory circuit to test itself by automatically generating test patterns to stimulate the circuit and then evaluating the response. This technique shortens the testing time by avoiding the need to send test data to and from a RAM via scan-chains or other intervening logic.
The testing time of a BIST March algorithm is defined in part by the number of read/write operations it contains. The operations or steps, when multiplied by the total number n of distinct addresses (each containing one or more bits or cells) in a memory array, is part of the length component of the testing time. The testing time may be measured in total clock cycles needed to complete the test, where the clock cycles are a function in part of the algorithm length.
In addition, BIST March algorithms may be custom designed for test
Kim Ilyoung
Zorian Yervant
Beausoliel, Jr. Robert W.
Elisca Pierre E.
Lucent Technologies - Inc.
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