Optimize global net timing with repeater buffers

Details Optimize global net timing with repeater buffers Optimize global net timing with repeater buffers

2000-07-20

2004-01-27

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06684373

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of computer aided design tools used for designing integrated circuits.
COPYRIGHT NOTICE/PERMISSION
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data as described below and in the drawings hereto: Copyright© Silicon Graphics Incorporated, 2000. All Rights Reserved.
BACKGROUND OF THE INVENTION
Electrical engineers use computer aided design (CAD) tools to design integrated circuits. The integrated circuit design process includes constructing the integrated circuit design out of simple circuits (e.g., “standard cells”) that are electrically connected together using wire interconnects. The CAD tool stores the standard cells and connections between them in well-known databases called “netlists.” A chip manufacturing foundry uses the netlist as input to build the physical integrated circuit.
As part of the design process, the CAD tool “places” and “routes” design information within a netlist using placing and routing processes (also called placers and routers) that are typically software programs executed by the CAD tool. The placer determines the optimum location of each standard cell within the integrated circuit layout on the semiconductor surface. The placer optimizes the placement location to reduce the distance between standard cells that are electrically connected to each other by wire interconnects (e.g., input/output lines). This is done to both (1) minimize the semiconductor area consumed by the integrated circuit; and (2) minimize the lengths of wire interconnects to reduce net capacitance within the design. The router optimizes the routing of input/output lines between connected standard cells, so that areas of the integrated circuit layout do not become overly congested by input/output lines and so that the timing of signals on the wire interconnects is minimized.
It is critical that the timing of signals on the wire interconnects meet the timing goal of the design, which is that operations will fit within one clock cycle. If operations do not fit within a clock cycle, the engineer must redesign the logic, which is expensive and time consuming. Thus, there is a need for a system that will automatically design the wire interconnects so that the timing goal is met.
SUMMARY OF THE INVENTION
The present invention provides solutions to the above-described shortcomings in conventional approaches, as well as other advantages apparent from the description below.
The present invention provides a method, system, and program product for designing an electronic circuit. The electronic circuit has a source component, a sink component and a wire connecting the source and sink components. In one aspect, the wire is divided into wire segments and repeater buffers are added to connect the wire segments. The number of repeater buffers is based on the calculated delay of the global net. In another aspect, the metal routes of the wire are widened to reduce delays on a global net. Thus, the invention automatically designs wire interconnects in an electronic circuit, so that the timing goal of the circuit is met, and operations in the electronic circuit will complete within one clock cycle.


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