Optimizations to receive packet status from fifo bus

Details Optimizations to receive packet status from fifo bus Optimizations to receive packet status from fifo bus

1999-12-28

2003-10-07

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S052000, C711S100000

Reexamination Certificate

active

06631430

ABSTRACT:

BACKGROUND OF THE INVENTION
A network device receives packets of information from a communication media access control device, e.g., an Ethernet controller. Each packet may contain data and the destination address of that data. Each receiving port of the device has a “ready signal” which indicates that a predetermined number of bytes or the last byte of the packet has been received. The predetermined number of bytes is usually
64
because that is the size of a minimum Ethernet packet. A high percentage of Ethernet packets (approximately 80%) are minimum length packets, e.g., 64 bytes. Optimizing for 64 byte packets by requesting 64 bytes increases the bandwidth of the processor.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method is described of receiving bytes of data from a media device includes issuing N consecutive requests, each for M bytes, to the media device and receiving N-
1
responses of M bytes of data from the media device.


REFERENCES:
patent: 5392391 (1995-02-01), Caulk, Jr. et al.
patent: 5392412 (1995-02-01), McKenna
patent: 5459842 (1995-10-01), Begun et al.
patent: 6345334 (2002-02-01), Nakagawa et al.
patent: 6415338 (2002-07-01), Habot

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