Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2003-10-06
2009-02-17
Auve, Glenn A (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S269000
Reexamination Certificate
active
07493435
ABSTRACT:
A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a single default SMI handler as a wake-up vector to the second processor, and may patch an instruction pointer to a non-aligned address during the handling of the SMI with the second processor to forgo the traditional extra aligned memory allocation. In addition, one may use unified handler code to handle software generated SMIs on both the first and second processors and may use exit SMM directly after handling a hardware SMI to save execution time.
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Cooper Barnes
Kobayashi Grant H.
Auve Glenn A
Intel Corporation
McAbee David P.
Vu Trisha
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