Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1998-11-13
2001-09-18
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S424000, C438S308000
Reexamination Certificate
active
06291327
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to methods for fabricating semiconductor integrated circuits such as memory devices and more particularly, it relates to a method of minimizing the problem of source/drain shorts in sub-micron shallow trench isolation (STI) technology employed in semiconductor integrated circuit fabrication of memory devices.
2. Description of the Prior Art
As is generally known, in the manufacturing of semi-conductor integrated circuits there is typically required isolation of devices (active regions) from one another which are formed on a semiconductor substrate. One such isolation technique is known as LOCOS (local oxidation of silicon) where an isolation region is grown on the substrate between the active regions by thermal oxidation. However, in view of the advances made in semiconductor integrated circuit technology and reduction of device sizes so as to achieve higher density, it has been found that a newer isolation method referred to as “shallow trench isolation” (STI) has become the replacement for the conventional LOCOS technology for sub-micron process technology. In the basic STI technology, there is involved the etching of the semiconductor substrate in order to form trenches and thereafter the re-filling of the trenches with an insulating material so as to produce an isolation region.
While it is desirable to use silicon dioxide layers as trench fill dielectric layers within advanced integrated circuit fabrication, it is generally known that such trench-refilling oxide may shrink during subsequent fabrication steps (e.g., thermal annealing) which will cause mechanical stress in the active silicon substrate. This mechanical stress is believed to cause the generation of dislocations or defect sites in the active substrate. This problem is discussed in a paper entitled “Mechanical Stress Induced MOSFET Punch-Through and Process Optimization for Deep Submicron TEOS-O
3
Filled STI Device,” by K. Ishimaru et al., 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 123-124.
Further, this generation of dislocations or defect sites in the active substrate was found to enhance doping diffusion, which will cause other undesirable effects. For example, in one case investigated a higher leakage current was found to exist between the source and drain regions of a transistor device formed during subsequent process steps in the substrate, thereby resulting in a lower product yield of the manufacturing operation. It is believed that the failure mechanism is due to the impurities implanted to form the highly-doped source/drain regions diffusing into the channel region and thus causing the channel width of the transistor to decrease. Consequentially, the leakage current will be increased and thus can cause “shorting” of the source and drain regions.
In co-pending application Ser. No. 09/192,096 filed on Nov. 13, 1999 and entitled “Reduction of Mechanical Stress in Shallow Trench Isolation Technology”, there are disclosed various process fixes for eliminating mechanical stress by either, (a) forming a trench with a more sloped and smooth profile, (b) limiting the trench depth to be less than 0.4 &mgr;m, (c) reducing or increasing the trench densification temperature, and/or (d) performing the densification step after chemical-mechanical polishing. This application Ser. No. 09/192,096 is assigned to the same assignee as the present invention and is hereby incorporated by reference. As an alternative to these aforementioned process fixes, the inventors of the present invention have developed another way to minimize the problem of source/drain shorts by performing simply modifications to the STI process.
Accordingly, it would be still desirable to provide a method of minimizing the problem of source/drain shorts in current standard STI process on a more effective and efficient basis. This is achieved in the present invention by reducing the rapid thermal annealing (RTA) temperature so as to minimize the enhanced diffusion from the source and drain regions to the channel region underneath the gate area. Further, in order to compensate for the problem of poly depletion in the gate area caused by the lower RTA temperature, the energy level used to implant the source/drain regions is made higher.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a method of minimizing the problem of source/drain shorts in a standard STI process which overcomes the problems of the prior art.
It is an object of the present invention to provide a method of minimizing source/drain shorts in a standard STI process which can be implemented with only minor modifications to the same.
It is another object of the present invention to provide a method of minimizing source/drain shorts in a standard STI process which includes reducing the RTA temperature so to lower enhanced diffusion from the source/drain regions.
It is still another object of the present invention to provide a method of minimizing source/drain shorts in a standard STI process which further includes raising the energy level used for implanting the source/drains so as to compensate for poly depletion in the gate area.
In accordance with a preferred embodiment of the present invention, there is provided a method of minimizing source/drain shorts in a standard shallow trench isolation (STI) process. A plurality of trenches are formed in a semiconductor substrate so as to create isolation regions to electrically isolate at least a pair of first and second active NMOS areas formed in the substrate from each other. First and second gate electrodes are formed on the top surface of the substrate and overlies respectively the first and second active NMOS areas.
Impurity ions are implanted into the first and second active NMOS areas with the first and second gate electrodes acting as masks so as to form N-type lightly-doped drain regions. Sidewall spacers are formed on each side of the first and second gate electrodes. The impurity ions are implanted into the first and second active NMOS areas with the first and second gate electrodes and the sidewall spacers acting as masks so as to form N-type highly-doped source/drain regions. A rapid thermal annealing process is performed at a temperature of less than 1000° C. so as to activate the highly-doped source/drain regions.
REFERENCES:
patent: 5538906 (1996-07-01), Aoki
patent: 5899714 (1999-05-01), Farrenkopf et al.
patent: 5981347 (1999-11-01), Kuo et al.
patent: 5998284 (1999-12-01), Azuma
patent: 6040019 (2000-03-01), Ishida et al.
Li Xiao-Yu
Mehta Sunil D.
Schmidt Christopher O.
Tu Robert H.
Chin Davis
Lattice Semiconductor Corporation
Pyonin Adam
Zarabian Amir
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