Optimization of routing layers and board space requirements...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S614000, C257S692000

Reexamination Certificate

active

07816247

ABSTRACT:
A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are arranged in an array of rows and columns. At least one edge of a perimeter of the array is not fully populated with conductive pads. Spaces created in the edge by missing conductive pads create additional routing channels for signals from conductive pads within the array to be routed external to the array through the edge. A land pattern may have routing channels on one or more layers of a printed circuit board. In such a multi-layer land pattern, spaces can be created in edges on any number of the layers. Furthermore, corner pad arrangements having known routing channel characteristics can be used in any number of corners of a land pattern that incorporates spaces in an edge.

REFERENCES:
patent: 5729894 (1998-03-01), Rostoker et al.
patent: 6150729 (2000-11-01), Ghahghahi
patent: 6194668 (2001-02-01), Horiuchi et al.
patent: 6229099 (2001-05-01), Horiuchi et al.
patent: 6285560 (2001-09-01), Lyne
patent: 6323434 (2001-11-01), Kurita et al.
patent: 6489574 (2002-12-01), Otaki et al.
patent: 6545876 (2003-04-01), Kwong et al.
patent: 6689634 (2004-02-01), Lyne
patent: 6762366 (2004-07-01), Miller et al.
patent: 0 100 657 (1984-02-01), None
patent: 0 883 182 (1998-12-01), None
patent: 0 928 029 (1999-07-01), None
patent: 1 085 571 (2001-03-01), None
patent: 1 087 440 (2001-03-01), None
“V54C3256164VBUC/T Low Power 256Mbit SDRAM 3.3 Volt, 54-Ball SOC BGA 43-PIN TSOPII X 16,”Mosel Vitelic Corp., Rev. 1.1 Feb. 2003, pp. 1-45.
Vern Solberg, “Design for BGA and CSP, Component Standards and PCB Design Guidelines,”Tessera Technologies, Inc. San Jose, CA, (Date unknown), 22 pages.
Intel Flash Memory Chip Scale Package User's Guide, “Manufacturing Considerations,” Intel Corporation, (1999) pp. 21-30.
“JEDEC Design Standard, Design Requirements for Outlines of Solid State and Related Products,” JEDEC Publication 95, Design Guide 4.5, JEDEC Solid State Technology Association, Aug. 2001, 19 pages.
“Altera Device Package Information,” Altera Corporation, May 2001, version 9.1, pp. 1-69.
Kuzawinski, Mark et al. “Effects of Fine Pitch BGA Grids on Module and Card Design,”IBM Corporation, Endicott, NY, pp. 91-99.
“Programming Adapter Specification,” Emulation Technology, Inc., Santa Clara, CA, Item 6540014BG9X86YA, May 3, 2000, one page.
Tom Hausherr, 'Metric Via Fanout BGA's;IPC Designers Council, (date unknown) 18 pages.
“PowerPC 750FX-IBM's 1 Ghz PowerPC Microprocessor,” IBM Power PC Processor News, IBM Corporation, Oct. 2001, 4 pages.
Joseph Fjelstad, “Exploiting the Opportunity of Area Array Packaging” Tessera Technologies, Inc., first published inSemiconductor Intemational,1998, 6 pages.
“TVM-288F uZ™ Fold-Over Test Vehicle with DRAM Interface,” Tessera Technologies, Inc:, 2 pages (2002).
“MTXC Package Information,” Intel Corporation, pp. 392-394 (date unknown).
Toshiba MOS Digital Integrated Circuit (Tentative), TC59M818DMB-30,-33,-40, Toshiba Corporation, Feb. 28, 2003, 55 pages.
Mechanical Data, GHK (S-PBGA-N209), Plastic Ball Grid Array, Oct. 2003, Copyright 2003, Texas Instruments Incorporated, 2 pages.
U.S. Appl. No. 10/651,164, filed Aug. 29, 2003, Seaman et al.
Mechanical Data, GHK (S-PBGA-N257), Plastic Ball Grid Array, Oct. 2003, Copyright 2003, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG091B—Dec. 1998—Revised Aug. 2002), GJG (S-PBGA-N257), Plastic Ball Grid Array, Aug. 2002, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG092B—Apr. 1998—Revised Jun. 2002), GHZ (S-PBGA-N151), Plastic Ball Grid Array, Dec. 2001, Copyright 2002 Texas Instruments Incorporated, 2 pages.
U.S. Appl. No. 10/921,134, filed Aug. 19, 2004, Seaman et al.
U.S. Appl. No. 10/921,181, filed Aug. 19, 2004, Seaman et al.
U.S. Appl. No. 10/921,225, filed Aug. 19, 2004, Seaman et al.
U.S. Appl. No. 10/921,914, filed Sep. 29, 2004, Seaman et al.
Mechanical Data, GHK (S-PBGA-N288), Plastic Ball Grid Array, Oct. 2003, Copyright 2003, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GZA (S-PBGA-N257), Plastic Ball Grid Array, Jan. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG169B—Oct. 2000—Revised Aug. 2002), GPH (S-PBGA-N181), Plastic Ball Grid Array, Aug. 2002, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG170B—Oct. 2000—Revised Aug. 2002), GPH (S-PBGA-N205), Plastic Ball Grid Array, Aug. 2002, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG171B—Oct. 2000—Revised Aug. 2002), GPH (S-PBGA-N241), Plastic Ball Grid Array, Aug. 2002, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG179A—Feb. 2001—Revised Jan. 2002), GZG (S-PBGA-N289), Plastic Ball Grid Array, Nov. 2001, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG304—Aug. 2002), GPH (S-PBGA-N173), Plastic Ball Grid Array, Aug. 2002, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GVL (S-PBGA-N289), Plastic Ball Grid Array, Oct. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GVM (S-PBGA-N289), Plastic Ball Grid Array, Jul. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GVL (S-PBGA-N318), Plastic Ball Grid Array, Oct. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GZA (S-PBGA-N291), Plastic Ball Grid Array Package, Jan. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GHK (S-PBGA-N306), Plastic Ball Grid Array, Oct. 2003, Copyright 2003, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GWE (S-PBGA-N289), Plastic Ball Grid Array, Jun. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GWG (S-PBGA-N241), Plastic Ball Grid Array, Aug. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG063C—Mar. 1998—Revised Jan. 2002), GZG (S-PBGA-N176), Plastic Ball Grid Array, Nov. 2001, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Mechanical Data, GVL (S-PBGA-N293), Plastic Ball Grid Array, Oct. 2004, Copyright 2004, Texas Instruments Incorporated, 2 pages.
Mechanical Data, (MPBG087B—Dec. 1998—Revised Aug. 2002), GJG (S-PBGA-N209), Plastic Ball Grid Array, Aug. 2002, Copyright 2002, Texas Instruments Incorporated, 2 pages.
Preliminary Amendment filed Aug. 19, 2004 in U.S. Appl. No. 10/921,134.
Preliminary Amendment filed Aug. 19, 2004 in U.S. Appl. No. 10/921,181.
Preliminary Amendment filed Aug. 19, 2004 in U.S. Appl. No. 10/921,225.
Preliminary Amendment filed Sep. 29, 2004 in U.S. Appl. No. 10/951,914.
European Search Report for International Application No. 04002178.4 mailed on May 17, 2004.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Optimization of routing layers and board space requirements... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimization of routing layers and board space requirements..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimization of routing layers and board space requirements... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4172679

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.