Optimization of digital designs

Details Optimization of digital designs Optimization of digital designs

2005-11-04

2009-11-24

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07624368

ABSTRACT:
An application specific integrated circuit is optimized by translating a first representation of its digital design to a second representation. The second representation includes multiple syntactic expressions that admit a representation of a higher-order function of base Boolean values. The syntactic expressions are manipulated to form a third representation of the digital design.

REFERENCES:
patent: 4792909 (1988-12-01), Serlet
patent: 5128871 (1992-07-01), Schmitz
patent: 5299204 (1994-03-01), Daniel
patent: 5406497 (1995-04-01), Altheimer et al.
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5581202 (1996-12-01), Yano et al.
patent: 5712792 (1998-01-01), Yamashita et al.
patent: 5724251 (1998-03-01), Heavlin
patent: 5734582 (1998-03-01), Bertolet et al.
patent: 5801551 (1998-09-01), Lin
patent: 5867396 (1999-02-01), Parlour
patent: 5872716 (1999-02-01), Yano et al.
patent: 5923189 (1999-07-01), Sasaki et al.
patent: 6049232 (2000-04-01), Sasaki et al.
patent: 6124736 (2000-09-01), Yamashita et al.
patent: 6243849 (2001-06-01), Singh et al.
patent: 6259276 (2001-07-01), Sasaki et al.
patent: 6260185 (2001-07-01), Sasaki et al.
patent: 6313665 (2001-11-01), Sasaki et al.
patent: 6313666 (2001-11-01), Yamashita et al.
patent: 6320421 (2001-11-01), Akita et al.
patent: 6323690 (2001-11-01), Yamashita et al.
patent: 6356118 (2002-03-01), Rikino et al.
patent: 6359468 (2002-03-01), Park et al.
patent: 6388474 (2002-05-01), Sasaki et al.
patent: 6400183 (2002-06-01), Yamashita et al.
patent: 6433588 (2002-08-01), Yamashita et al.
patent: 6445214 (2002-09-01), Sasaki et al.
patent: 6486708 (2002-11-01), Yamashita et al.
patent: 6505322 (2003-01-01), Yamashita et al.
patent: 6532581 (2003-03-01), Toyonaga et al.
patent: 6536028 (2003-03-01), Katsioulas et al.
patent: RE38059 (2003-04-01), Yano et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6564361 (2003-05-01), Zolotykh et al.
patent: 6564364 (2003-05-01), Dahl et al.
patent: 6588006 (2003-07-01), Watkins
patent: 6598209 (2003-07-01), Sokolov
patent: 6651223 (2003-11-01), Yamashita et al.
patent: 6690206 (2004-02-01), Rikino et al.
patent: 6696864 (2004-02-01), Yamashita et al.
patent: 6820242 (2004-11-01), Yamashita et al.
patent: 6845349 (2005-01-01), Sasaki et al.
patent: 7190376 (2007-03-01), Tonisson
patent: 2002/0178432 (2002-11-01), Kim et al.
patent: 2003/0085738 (2003-05-01), Maki et al.
patent: 2003/0200510 (2003-10-01), Whitaker et al.
patent: 2003/0204822 (2003-10-01), Whitaker et al.
Kazuo Yano et al.,Top-Down Pass-Transistor Logic Design, IEEE Journal of Solid-State Circuits, vol. 31, No. 6, Jun. 1996, pp. 792-803.

Affiliated with

Also associated with

Rating

Optimization of digital designs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimization of digital designs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimization of digital designs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4063454