Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-05-02
2004-11-30
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C700S110000, C700S120000, C700S121000
Reexamination Certificate
active
06826738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of manufacturing of semiconductor devices, and more specifically to a process to print fields on a wafer in a way that increases the semiconductor manufacturer (FAB) throughput, profitability and/or product reliability.
2. Background Art
The annual sales of the semiconductor industry are around $152,000,000,000 to $200,000,000,000 a year. New semiconductor manufacturing plants (FABs) cost from $2 billion to more than $10 billion. Large increases in fabrication cost are primarily driven by an increase in equipment costs. Algorithms that increase a FAB's productivity and/or profitability, even by a small percentage, will reduce the cost of a die and will significantly increases the profitability of the semiconductor company.
Today the following model is typically used to calculate the cost of a die:
C
die
=C
wafer
/(
N
dies on a wafer
*Y
wafer
)
where:
C
die
is the cost of a die;
C
wafer
is the cost to manufacture a wafer;
N
dies
on a wafer is the number of dies on a wafer; and
Y
wafer
is the wafer yield.
Prior approaches to laying out dies on a wafer typically assume uniform manufacturing cost for placing reticles on the wafer. The objective for the prior optimization algorithm is to reduce the manufacturing cost by reducing the number of reticle fields and increasing the number of gross dies. Furthermore, new process technologies require that fields be printed on a wafer, even if they will not produce any good-yielding dies. Prior art optimization techniques, for example, as disclosed in U.S. Pat. Nos. 5,874,189 and 6,016,391, will eliminate the reticle fields that do not produce good-yielding dies. However, by doing so they will reduce the yield of the dies placed on the wafer. Furthermore, the prior approaches assume uniformity of yield and product performance across the wafer and uniformity in the manufacturing cost. As a result, they may increase the number of dies placed on the wafer, but the total dies shipped to the customers will be reduced. Using the prior approaches will thus cause loss in yield, product reliability, FAB throughput and FAB profitability.
SUMMARY OF THE INVENTION
One object of the present invention is to print fields on the wafer in a way that maximizes the number of dies shipped to customers, the FAB throughput and profitability.
Another object of the invention is place fields on the wafer in a way that maximizes the product reliability produced by the FAB.
A further object of the invention is to define the die shape and the reticle shape to maximize product reliability, FAB profitability and productivity.
Other objects and advantages of the present invention will become apparent from the description below, taken in connection with the accompanying drawings, wherein, by way of illustration and example, embodiments of the present invention are disclosed.
One embodiment of the invention comprises a method of optimizing production of semiconductor devices from a wafer, comprising the following steps. At least one effect on at least one aspect of production (e.g., yield, cost, profitability, etc.) due to at least one manufacturing component (where a manufacturing component is defined to be a process or machine used in the manufacture of semiconductor devices on the wafer) is determined. A user inputs data corresponding to at least one optimization target. Then, optimization is performed based on the determined effect(s) and the data input by the user to determine a layout of semiconductor devices on the wafer.
In further embodiments, the inventive method may be embodied in the form of software on a computer-readable medium or in the form of a computer system running such software.
In one preferred embodiment of the invention, the process determines layout of fields on a wafer in a way that increases the semiconductor manufacturer (FAB) throughput, profitability and product reliability. The process may include a process to base the placement on non-uniformity of the yield and product performance distribution across the wafer, a process to base the placement on non-uniformity of cost associated with the production of each die on the wafer, and/or a process to base the placement on non-uniformity of the selling price of different dies placed on the wafer. Product reliability may also be integrated into the placement optimization process.
In a further preferred embodiment of the invention, the inventive process may comprise steps of defining shapes and/or aspect ratios of dies and/or reticles in a way that increases the semiconductor manufacturer (FAB) throughput, profitability and product reliability.
The process may include placing semiconductor chips (dies) on the wafer, determining the die aspect ratio, determining the chips' shapes, defining design rules, and/or aligning the FAB equipment and FAB manufacturing environment.
Definitions
In describing the invention, the following definitions are applicable throughout (including above).
A “computer” refers to any apparatus that is capable of accepting a structured input, processing the structured input according to prescribed rules, and producing results of the processing as output. Examples of a computer include: a computer; a general purpose computer; a supercomputer; a mainframe; a super mini-computer; a mini-computer; a workstation; a microcomputer; a server; an interactive television; a hybrid combination of a computer and an interactive television; and application-specific hardware to emulate a computer and/or software. A computer can have a single processor or multiple processors, which can operate in parallel and/or not in parallel. A computer also refers to two or more computers connected together via a network for transmitting or receiving information between the computers. An example of such a computer includes a distributed computer system for processing information via computers linked by a network.
A “computer-readable medium” refers to any storage device used for storing data accessible by a computer. Examples of a computer-readable medium include: a magnetic hard disk; a floppy disk; an optical disk, like a CD-ROM or a DVD; a magnetic tape; a memory chip; and a carrier wave used to carry computer-readable electronic data, such as those used in transmitting and receiving e-mail or in accessing a network.
“Software” refers to prescribed rules to operate a computer. Examples of software include: software; code segments; instructions; computer programs; and programmed logic.
A “computer system” refers to a system having a computer, where the computer comprises a computer-readable medium embodying software to operate the computer.
A “network” refers to a number of computers and associated devices that are connected by communication facilities. A network involves permanent connections such as cables or temporary connections such as those made through telephone or other communication links. Examples of a network include: an internet, such as the Internet; an intranet; a local area network (LAN); a wide area network (WAN); and a combination of networks, such as an internet and an intranet.
REFERENCES:
patent: 5498579 (1996-03-01), Borodovsky et al.
patent: 5874189 (1999-02-01), Stroh et al.
patent: 6016391 (2000-01-01), Facchini et al.
patent: 6070004 (2000-05-01), Prein
patent: 6341241 (2002-01-01), Mugibayashi et al.
patent: 6393602 (2002-05-01), Atchison et al.
patent: 6591409 (2003-07-01), Kamath et al.
patent: 6703170 (2004-03-01), Pindo
patent: 2002/0123818 (2002-09-01), Yamada et al.
Sarma et al., “Wafer Level Reliability Application to Manufacturing of High Performance Microprocessor”, IEEE International Integrated Reliability Workshop, Oct. 20, 1996, pp. 77-81.
Kik Phallaka
Morrison & Foerster / LLP
PDF Solutions, Inc.
Smith Matthew
LandOfFree
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