Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
1999-09-30
2001-07-17
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C156S345420, C216S084000, C216S088000, C438S014000, C438S692000, C438S745000
Reexamination Certificate
active
06261851
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a chemical mechanical planarization (“CMP”) process and, more particularly, improvements with the monitoring of the CMP process in connection with the removal of oxide films having stops on films containing silicon nitride.
BACKGROUND OF THE INVENTION
Fabrication techniques for the manufacture of the wafers for integrated circuits involve the formation of a series of layers upon a silicon wafer. In the typical manufacturing process, a wafer undergoes a photo resist step followed by photo lithography. Next, the wafer is etched, then stripped and then subjected to a diffusion step. The CMP process is then used to planarize the surface of the wafer before the wafer is subjected to repeated iterations of these steps which build multi layers on the wafer. CMP has been described as “wet sanding” the surface of the wafer to polish the surface of the wafer smooth, and the object of the planarization process is to achieve a highly uniform planar surface on the wafer.
The precise detection of the endpoints during the CMP process is a critical step in the processing of such multilayered integrated circuits. It is desirable to have each layer on the wafer extremely flat or planar before the creation of each successive layer because improving the surface both enhances the optical lithograph process and improves the metal interconnect reliability between layers. Before the incorporation of CMP processes, the topography of the wafer is irregular and, as a result, a lithographic image formed on the wafer may be out of focus. The lack of focus will interfere with the subsequent etching steps which may lead to problems with the interconnects between layers and may result in degraded chip performance and decreased yields. Further, since the deposition and etchback tolerances associated with large film are cumulative, any non-planarity of the resist is replicated in subsequent oxide surfaces.
The typical apparatus used in the CMP process includes a holder for the wafer which is held on a carrier. This assembly is rotated and pushed down on an abrasive pad mounted on a platen which rotates on a different axis and in an opposite direction from the carrier. A chemically active slurry containing small abrasive particles is introduced to the rotating pad which contributes both chemical and mechanical elements to the processes. When the CMP process is directed to an oxide layer on the wafer, the slurry contains fumed silica suspended in an aqueous solution containing KOH and having a pH of 10.5. The pH is maintained at high levels to keep the fumed silica particles suspended in the solution. When the slurry is intended for the polishing of a metallic layer, the slurry typically contains oxidizers and has a low pH (0.5 to 4). Typically, the particles in a slurry are chemically inert and are usually alumina, silica or both. New slurry is continuously introduced to the process as old slurry is removed. The old slurry will contain the abraded particles of both the pad and the wafer and end products of the chemical reaction. Following the CMP process, the wafer is buffed to remove any slurry and cleaned to provide a smooth final finish to the wafer.
The CMP process is used for the planarization of both dielectric and metallic layers. The CMP process, when applied to metallic layers' surfaces, involves a chemical reaction at the surface of the wafer which leaves the surface more susceptible to mechanical abrasion by the particles suspended in the slurry.
There are a wide number of variables which can influence the rate and uniformity of the planarization operation. Mechanical variables involved in the process include the rotational speeds of the platen and carrier, the back pressure applied to the pad, the profile of the pad and carrier, and the downward force applied to the platen. Further, the various components used in the process contribute to yet additional variables in the operation. Typically, the polishing pad on the platen is made of polyurethane and the surface is much rougher than the typical wafer being polished. Variation in the pads used for the removal or other consumables used in the process can significantly alter the rate of removal of layers on the wafer. In addition to the mechanical control parameters, the characteristics of the slurry add a number of additional variables, including the particle distribution, temperature, pH and its rate of introduction. Changes in the slurry temperature can stiffen the pad, thereby increasing removal rates and also affect the chemical dynamics. In addition to calculating the effects of the numerous variables identified above, the process itself is dynamic, further contributing to difficulties in precisely controlling the process to achieve repeatable results. In this regard, the CMP pad wears at an exponential rate when first put in use and then later wears in a linear fashion. As the CMP polishing pad ages, its removal of material from the wafer is not always uniform. Warpage of the wafer which can be caused by repeated thermal cycles in the fabrication process can also contribute to variations in the rate of removal of layers in the CMP process.
The total polishing time will depend on the initial film thickness and the film removal rate. The removal rate is dependant on the various process parameters identified above as well as variations in the depositing techniques which form the respective layers on the wafer. During the development of a new device, considerable time is expended selecting the optimal mechanical parameter for the CMP process, including the polishing pad features, the slurry characteristics, and the speeds and force between the platen and carrier. This process has relied heavily upon experimental data relating to uniformity and film removal rates.
In view of the configuration of the equipment, real time in situ determination of the CMP process endpoint presents difficulties. Merely attempting to precisely repeat operating conditions based upon historical results does not achieve reliable or satisfactory results. Removal of the wafer from the polishing table for periodic inspection and analysis significantly reduces the throughput and introduces further variables into the process, thereby altering the polishing rate.
In response to the need to monitor and control the progress of the CMP process, and more particularly, to accurately identify the endpoint of the process, a number of in situ techniques have been developed to monitor the rate of removal. For layers having metal components, a number of techniques have been directed at measuring the changes in the capacitance of the wafer. With particular respect to the measurement of dielectric layers where the foregoing technique is ineffective, efforts have included (1) attempting to measure changes in frictional forces between the pad and the wafer between layers, (2) providing a window through the polishing pad to allow for the measurement of changes in optical properties of the wafer between layers, and (3) sensing acoustical changes between the polishing pad and the various layers.
Efforts have also been addressed at reducing irregularities in the topography during the fabrication steps, including BPSG reflow, spin-on filming, resist etchback techniques, electroncyclotron resonant deposition (ECR), and high density plasma (HDP); however, these techniques have not been able to match CMP in the quality of planarity of the surface across the entire wafer. Techniques which involve baking the wafer at very high temperatures to allow the oxide material which has been deposited to liquify and reflow to increase the level degree of planarization, usually require the introduction of undesirable impurities to the oxide to lower the temperature so that the oxide will become vitrified. Moreover, repeated exposure ofthe device to very high temperatures can effect that performance of the device. When multiple levels of connection are desired in a device, non-CMP based methods of planarization alone are often inadequate. CMP provides a much mor
Gilhooly James A.
Li Leping
Morgan, III Clifford O.
Wei Cong
Anderson Jay H.
International Business Machines - Corporation
Powell William A.
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