Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-08-26
2008-09-30
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S134000, C711S154000
Reexamination Certificate
active
07430639
ABSTRACT:
The present invention includes storing in a main memory data block tags corresponding to blocks of data previously inserted into a buffer cache memory and then evicted from the buffer cache memory or written over in the buffer cache memory. Counters associated with the tags are updated when look-up requests to look up data block tags are received from a cache look-up algorithm.
REFERENCES:
patent: 5944815 (1999-08-01), Witt
patent: 2005/0138289 (2005-06-01), Royer et al.
Carr, et al., “WSClock—A simple and effective algorithm for virtual memory management”,Proc. Eighth Sump. Operating System Principles, (1981), pp. 87-95.
Denning, “Working sets past and present”,IEEE Trans Software Engineering, vol. SE-6, No. 1, (1980), pp. 64-85.
Jiang, et al., “LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance”,Proc. ACM Sigmetrics Conf., (2002).
Johnson, et al., “2Q: A low overhead high performance buffer management replacement algorithm”,Proceedings of the 20th VLDB Conf., Santiago, Chile, (1994), pp. 439-450.
Lee, et al., “LRFU: A spectrum of policies that subsumes the least recently used and least frequently used policies”,IEEE Trans. Computers, vol. 50, No. 12, (2001), pp. 1352-1360.
Megiddo, et al., “ARC: A self-tuning, low overhead replacement cache”,USENIX File&Storage Technologies Conference(FAST), (Mar. 2003).
O'Neil, et al., “The LRU-K page replacement algorithm for database disk buffering”,Proc. 1993 ACL Sigmod International Conference on Management of Data, Washington, DC, (May 1993), pp. 297-306.
Zhou, et al., “The multi-queue replacement algorithm for second level buffer caches”,Proceedings of the 2001 USENIX Annual Technical Conference, Boston, MA, (Jun. 2001).
Bali Naveen
Patel Naresh
Network Appliance Inc.
Thai Tuan V.
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