Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-03-31
2004-07-20
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S144000, C711S145000, C711S159000, C712S043000, C712S220000, C712S227000, C712S229000
Reexamination Certificate
active
06766419
ABSTRACT:
BACKGROUND
The present invention relates to a method and apparatus for providing software “hints” for the purposes of cache management in an integrated circuit.
As processor cycle times continue to decrease, management of memory latency and bus bandwidth becomes an increasingly important capability in computer systems. Contemporary processor designs often address these issues by providing on-chip or on-package cache memory. Some processors even provide multi-level cache hierarchies in which a lowest level cache, the cache closest to the processor core, is very fast but very small when measured against higher level caches. To improve hit rates and to avoid cache pollution, many processors also provide separate instruction and data caches, which enable higher hit rates due to increased code or data locality found in typical application's code and data streams. Unfortunately, the working set sizes of large applications continue to exceed the size of many current processor caches, even those with large multi-level cache systems.
Several processor designs have added instruction set extensions that permit both instruction and data prefetch instructions and/or hints. These prefetch instructions and hints allow software to initiate memory accesses early by identifying addresses of data that are likely to be needed by the software in future execution. Current prefetch instructions are either specified explicitly as data or code prefetch instructions or are specified indirectly on branch or load instructions. Currently existing prefetch hints and instructions enable software to specify a level of the memory hierarchy at which a specific data item should be allocated. This allows software that knows about the relative sizes of an application's working set and the processor's cache sizes to effectively allocate the working set in the appropriate cache level.
Current prefetch hints and instructions focus on allocation of cache lines from memory into the processor's memory hierarchy. However, they rely on the processor's built-in cache replacement policies to evict (and possibly write back) cache lines from the processor to memory. These hardwired replacement policies typically evict data on a least-recently-used, not-recently-used or random basis. In many situations, however, a software designer may know beforehand that a referenced data item is not going to be a likely candidate for re-use in the near future or ever. Consider a video decoding application by way of example. When a frame of data is decoded, the decoded image data typically is output from a processor for display. Once the decoded image data is output, it may have no further use within the processor's cache. Thus, any cache space occupied by such data could be evicted without performance loss within the processor. Currently, however, processor instruction sets do not provide a mechanism that permits software designers to identify data that is not likely to be used again during program execution.
Accordingly, there is a need in the art for an instruction set for a processor that permits a software designer to identify data that is not likely to be used during future program execution.
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Baxter Jeffrey
Zahir Achmed Rumi
Elmore Stephen
Kenyon & Kenyon
Kim Matthew
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