Optimal write conductors layout for improved performance in...

Details Optimal write conductors layout for improved performance in... Optimal write conductors layout for improved performance in...

2000-07-21

2001-05-22

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S171000, C365S158000

Reexamination Certificate

active

06236590

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to an optimal write conductor layout in a magnetic random access memory (MRAM). More specifically, the present invention relates to a write conductor layout wherein a width of a write conductor is made less than a width of a data storage layer and the width of the write conductor is contained entirely within the width of the data storage layer.
BACKGROUND ART
A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Located at a cross point of a word line and a bit line, each memory cell stores a bit of information as an orientation of a magnetization. The orientation of magnetization of each memory cell will assume one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of “1” and “0” The orientation of magnetization of a selected memory cell may be changed by supplying current to a word line and a bit line crossing the selected memory cell. The currents create magnetic fields that, when combined, can switch the orientation of magnetization of the selected memory cell from parallel to anti-parallel or vice versa. Because the word line and the bit line operate in combination to switch the orientation of magnetization of the selected memory cell (i.e. to write the memory cell), the word line and the bit line can be collectively referred to as write lines. Additionally, the write lines can also be used to read the logic value stored in the memory cell.
FIG. 1
illustrates a top plan view of a simplified prior art MRAM array
100
. The array
100
includes word lines
130
, bit lines
132
, and memory cells
120
. The memory cells
120
are positioned at each intersection of a word line
130
with a bit line
132
. In many MRAM designs, the write lines (
130
,
132
) are made the same width as the memory cell
120
as shown by a width dx for the bit lines
132
and a width dy for the word lines
130
. Consequently, the memory cells
120
have rectangular dimensions dx and dy that are defined by the widths of the write lines (
130
,
132
). Typically, the write lines (
130
,
132
) are arranged in orthogonal relation to one another and the memory cells
120
are positioned in between the write lines (
130
,
132
), as illustrated in
FIG. 1
b
. For example, the bit lines
132
can be positioned above the memory cells
120
and the word lines
130
can be positioned below.
FIGS. 2
a
through
2
c
illustrate the storage of a bit of data in a single memory cell
120
. In
FIG. 2
a
, the memory cell
120
includes an active magnetic data film
122
and a pinned magnetic film
124
which are separated by a dielectric region
126
. The orientation of magnetization in the active magnetic data film
122
is non-fixed and can assume two stable orientations as shown by arrow M
1
. On the other hand, the pinned magnetic film
124
has a fixed orientation of magnetization as shown by arrow M
2
. The active magnetic data film
122
rotates its orientation of magnetization in response to electrical currents applied to the write lines (
130
,
132
, not shown) during a write operation to the memory cell
120
. A first logic state of the data bit stored in the memory cell
120
is indicated when M
1
and M
2
are parallel to each other as illustrated in
FIG. 2
b
. For instance, when M
1
and M
2
are parallel a logic “1” state is stored in the memory cell
120
. Conversely, a second logic state is indicated when M
1
and M
2
are anti-parallel to each other as illustrated in
FIG. 2
c
. Similarly, when M
1
and M
2
are anti-parallel a logic “0” state is stored in the memory cell
120
. In
FIGS. 2
b
and
2
c
the dielectric region
126
has been omitted. Although
FIGS. 2
a
through
2
c
illustrate the active magnetic data film
122
positioned above the pinned magnetic film
124
, the pinned magnetic film
124
can be positioned above the active magnetic data film
122
.
The resistance of the memory cell
120
differs according to the orientations of M
1
and M
2
. When M
1
and M
2
are anti-parallel, i.e. the logic “0” state, the resistance of the memory cell
120
is at it highest. On the other hand, the resistance of the memory cell
120
is at its lowest when the orientations of M
1
and M
2
are parallel, i.e. the logic “1” state. As a consequence, the logic state of the data bit stored in the memory cell
120
can be determined by measuring it resistance. The resistance of the memory cell
120
is reflected by a magnitude of a sense current
123
(referring to
FIG. 2
a
) that flows in response to read voltages applied to the write lines (
130
,
132
).
In
FIG. 3
, the memory cell
120
is positioned between the write lines (
130
,
132
). The active and pinned magnetic films (
122
,
124
) are not shown in FIG.
3
. The orientation of magnetization of the active magnetic data film
122
is rotated in response to a current I
x
that generates a magnetic field H
y
and a current I
y
that generates a magnetic field H
x
. The magnetic fields H
x
and H
y
act in combination to rotate the orientation of magnetization of the memory cell
120
. In
FIG. 3
, the write lines (
130
,
132
) are shown having the same widths (dx and dy) as the memory cell
120
as previously mentioned in reference to
FIGS. 1
a
and
1
b.
Ideally, both of the write lines (
130
,
132
) should have widths (dx and dy) that are identical to their corresponding widths (dx and dy) on the memory cell
120
. Accordingly, the bit line
132
should have a width W
CV
in a vertical direction Y that is equal in width to a width W
DV
in the vertical direction Y of the memory cell
120
as illustrated in
FIG. 4
a
. Similarly, the word line
130
should have a width W
CH
in a horizontal direction X that is equal in width to a width W
DH
in the horizontal direction X of the memory cell
120
as illustrated in
FIG. 5
a.
However, due to misalignment between the write lines (
130
,
132
) and the memory cells
120
of the array
100
(see
FIGS. 1
a
and
1
b
), the word lines
130
and the bit lines
132
can be offset from the memory cells
120
. The misalignment can be caused by lithographic alignment inaccuracies that are inherent to the lithographic processes that are used to fabricate an MRAM device. In
FIG. 4
b
, the bit line
132
is offset from the memory cell
120
by an offset &dgr;. Similarly, in
FIG. 5
b
, the word line
130
is offset from the memory cell
120
by an offset &dgr;. The value of &dgr; will depend on the lithographic process used to fabricate the MRAM device. For instance, a state-of-the-art value of &dgr; can be on the order of 0.05 &mgr;m. That value for &dgr; can be quite substantial for sub-micron size memory cells.
One disadvantage of the offset &dgr; is a reduced magnetic field in those portions of the memory cell
120
that are not covered by the write lines (
130
,
132
) as shown by dashed lines
141
and
145
that encircle an exposed edge of the memory cell
120
in
FIGS. 4
b
and
5
b
respectively. As a result, the combined magnetic fields from the write lines (
130
,
132
) may not rotate the orientation of magnetization M
1
from a parallel orientation to an anti-parallel orientation or vice-versa during a write operation that selects the memory cell
120
.
Another disadvantage of the offset &dgr; is that a portion of the write lines (
130
,
132
) is positioned outside the width of the memory cell
120
as shown by cross-hatched regions
143
and
147
in
FIGS. 4
b
and
5
b
respectively. Consequently, the magnetic field generated by those portions is mainly wasted and cannot contribute to rotating the orientation of magnetization M
1
. Additionally, in extreme cases, the portion of the magnetic field produced by the double-hatched regions
143
and
147
can interfere with unselected bits of neighboring memory cells (not shown) thus causing data corruption of already written information in those neighboring memory cells.
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