Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-06-22
2003-11-04
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
Reexamination Certificate
active
06643746
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the field of uniform memory access systems, more particularly to the area of multi-channel memory access systems.
In the past, computer systems have utilized an arrangement where a multiple number of requestors accessed a memory through a single memory channel. As a result of these multiple requesters needing to access the memory system through a single memory channel, the speed of the process being run by the computer has not been optimal. Therefore, there is a desire for a memory system that will allow a multiple number of requesters to access the memory system simultaneously.
For example, in the area of computer graphics, application programs often utilize several buffers in the application program. Each of these buffers, e.g., a local buffer, a frame buffer, and a texture buffer are required to perform a graphics routine. Each of these buffers is designated a location in the memory system. However, in prior systems, an application could only access each buffer one at a time. To enhance the performance of the graphics application program, it would be desirable if a memory system existed that would allow both or all three buffers to be accessed simultaneously. While one can envision that each buffer could be stored in a separate memory system dedicated to that particular buffer, it would be desirable if an application that normally deals with one buffer could also access different buffers. Therefore, it is desirable that a unified memory system to be able to access each individual buffer should that be necessary.
In traditional approaches, multi-channel memory systems have typically not provided for unified memory architecture. In fact, application programs have been expected to split the logical buffers of the application physically over the different memory channels of the memory system. This reduces greatly the functionality of the system and may yield to subsequent degradation of the memory performance if transfers within logical buffers are required. The physical size of each memory channel also fixes the size of the logical buffers and their granularity. A system requiring a large logical buffer, or a logical buffer with uncommon granularity, may thus end up wasting a large amount of physical memory.
In the past, memory systems requiring support for unified memory architecture typically have made use of a single memory channel. However, the bandwidth of a single channel memory system can be considered to be approximately N times less than that of an N channel memory system (for a given data bus width).
While an alternative solution to multi-channels might be to increase the memory data bus width, this implies that accesses to memory are essentially sequential and contiguous, which is not the case in most applications with multiple request sources.
Therefore, current memory systems can be classified into two categories. The first is a single channel unified memory system, with a low bandwidth for a large pin count. The second is a multi-channel non-unified memory system that is functionally limited. Therefore, there is a desire for a flexible solution to this problem whereby an application can dynamically make use of multiple channels while keeping a fully unified memory architecture system.
SUMMARY OF THE INVENTION
The present invention provides a circuit for use in a Unified Memory Architecture system, the circuit comprising a memory of the Unified Memory Architecture system; a plurality of requesting devices; a plurality of channel selectors capable of receiving a command from at least one of said plurality of requesting devices for the Unified Memory Architecture system; a first memory channel coupled to each of said channel selectors that can provide access to a first area of address space of the memory; and at least one additional memory channel coupled to each of said channel selectors, the or each additional memory channel being capable of providing access to an additional address space of said memory, wherein the circuit is characterized by an arbiter capable of passing said command to a memory controller with a selector-tag for use when said command is a read request to identify the channel selector that routed the command to the memory channel; and wherein said arbiter, memory controller and memory channel used to pass said command are responsible for and capable of transmitting data both to and from said memory. Similarly, a method of operating the circuit is also provided by the invention.
The invention is advantageous in that a Universal Memory Architecture System can be implemented while allowing a plurality of requesters to access the Universal Memory Architecture System. In this manner, the speed of the memory system is enhanced, because the various requesters can access different areas of the memory simultaneously rather than serially. In addition, application programs running on processors of the requesters can optimize their performance by reallocating buffers used by the application program to different memory channels. In this fashion, the information of the buffers can be accessed simultaneously and the speed of the application program can be increased.
It is to be understood that the invention is not limited to the details disclosed but includes all such variations and modifications as fall within the spirit of the invention and the scope of the appended claims.
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Blakely , Sokoloff, Taylor & Zafman LLP
Creative Technology Ltd.
Ellis Kevin L.
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