Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1998-12-07
2001-08-21
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000
Reexamination Certificate
active
06278193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for manufacturing solid-state devices and more particularly to method of using alignment marks on one side of a chip to determine locations of pads on the other side of the chip and to align the chip pads with substrate pads.
2. Description of the Related Art
Chip attachment technologies such as solder reflow, thermo-compression, and conductive adhesives are becoming mainstream processes for chip or integrated circuit device attachment. The advantages of surface mounted chips and other devices are well known to those skilled in the art. The most demanding aspect of chip/substrate assembly is generally regarded to be chip placement relative to the supporting substrate or board.
It is difficult to place chips, such as flip chips and other surface mounted devices and packages, accurately since the signal and attachment pads are between the carrier package (or circuit board) and the chip/package during placement. In other words, the connection pads on the chip and the connection pads on the substrate are out of view during the alignment and attachment process.
Conventional alignment techniques include acquiring the chip I/O (input/output) side pattern and the substrate I/O pattern; superimposing the I/O patterns; centering and rotating the chip/substrate to best align the I/O patterns; placing the chip on the substrate; and in certain instances, verifying the connections between the chip and the substrate by electrically testing the connections and/or observing the relatively irregular chip edge. Superimposing the substrate I/O pattern and chip I/O pattern is generally performed using prisms, up and downward observation optics, or other similar well known techniques/devices.
Such conventional techniques and devices are expensive and difficult to use from both hardware and control logic standpoints. Further, the placement and confident verification requires high degrees of mechanical, optical, and control system sophistication.
Chips and other solid state devices are constantly being redesigned to pack more function into smaller device sizes, often resulting in high value devices that need to be accurately mounted to be economically viable. Present industry trends are moving in the direction of smaller and smaller I/O contacts on ever smaller centers. These trends increase demands on flip-chip tooling, placement accuracy and verification capability. Furthermore, in the case of non-solder reflow type attachment processes (e.g., thermo-compression or conductive adhesive) placement accuracy of better than 90% is required.
Therefore, there is a need to increase the accuracy of aligning the chip with the substrate while decreasing the cost, complexity and equipment requirements. The invention, described in detail below, produces a less expensive, less equipment intensive and more accurate alignment of the chip and substrate than can be attained with conventional structures and methods.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for aligning chips, such as flip chips and solid state packages, with their respective placement sites on substrates, which simplifies verification of proper alignment after placement and/or attachment.
In one embodiment, the invention involves a method of manufacturing semiconductor devices comprising providing a chip and a substrate, aligning the chip and the substrate and attaching the chip to the substrate, the aligning comprising providing at least one chip alignment mark on a first side of the chip (wherein the chip alignment mark corresponds to chip pads orientation on a second side of the chip) and aligning the alignment mark with substrate pads on the substrate.
The providing of the chip alignment mark may comprise forming crosshairs on the chip, forming at least one transparent area through the chip, forming at least one chip notch in the chip, or marking the chip with identification information. The aligning may include aligning the chip alignment mark with at least one substrate alignment mark on the substrate, aligning the chip alignment mark and the substrate alignment mark, aligning the chip transparent area with at least one dummy pad on the substrate, or aligning the chip notch with at least one substrate notch on the substrate.
Another embodiment of the invention involves an integrated circuit structure comprising a chip having at least one chip alignment mark on a first side of the chip (wherein the chip alignment mark corresponds to chip pads on a second side of the chip) and a substrate having substrate pads, wherein the substrate pads are aligned with the chip alignment mark.
The chip alignment mark may comprises cross-hairs on the chip, at least one transparent area through the chip, at least one chip notch in the chip, or identification information. The substrate may includes at least one substrate alignment mark aligned with the chip alignment mark, at least one dummy pad aligned with the chip transparent area, or at least one substrate notch aligned with the chip notch.
The invention simplifies the process of aligning chip pads with substrate pads by providing alignment markings which can be simultaneously or sequentially viewed from a single direction. Further, the alignment markings are chip-based and are not external to the chip. Thus, the invention dramatically simplifies the alignment process and reduces the need for prism-based alignment mechanisms, transparent substrates or other complicated and expensive conventional alignment technologies. Further, the invention reduces or eliminates the need for electrical alignment testing of the pad connections by providing alignment marks which remain visible from a single viewing location after the chip is attached to the substrate.
REFERENCES:
patent: 4941255 (1990-07-01), Bull
patent: 5237622 (1993-08-01), Howell
patent: 5311304 (1994-05-01), Monno
patent: 5389873 (1995-02-01), Ishii et al.
patent: 5457538 (1995-10-01), Ujiie
patent: 5459081 (1995-10-01), Kajita
patent: 5483174 (1996-01-01), Hembree et al.
patent: 5496777 (1996-03-01), Moriyama
patent: 5519535 (1996-05-01), Mok
patent: 5805421 (1998-09-01), Livengood et al.
patent: 5894172 (1999-04-01), Hyozo et al.
patent: 5943588 (1999-08-01), Watrobski et al.
patent: 62-22432-A (1987-01-01), None
patent: 1-184930-A (1989-07-01), None
patent: 1-199436-A (1989-08-01), None
patent: 3-276740-A (1991-12-01), None
patent: 6-196534-A (1994-07-01), None
Coico Patrick A.
Covell James H.
Blecker, Esq. Ira D.
International Business Machines - Corporation
McGinn & Gibb PLLC
Picardat Kevin M.
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