Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-14
2004-11-02
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S182000
Reexamination Certificate
active
06813758
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of integrated circuit design, and particularly to an optical proximity correction driven hierarchy.
BACKGROUND OF THE INVENTION
With the advance of technology and the increasing desires of consumers for increased functionality, designing integrated circuits is becoming increasingly more complicated. For example, with advanced manufacturing techniques, increasingly smaller circuit elements are utilized, enabling increased numbers of circuit elements to be included on a circuit. As the number of elements increases, measures taken to correct designs of the integrated circuit have become even more resource intensive to the point that it may take a significant amount of time to even perform one aspect of design verification, even employing multiple information handling systems.
For example, integrated circuits have a distinctive physical circuit layout employing various geometric elements to provide the circuit functionality. Typically, the physical layout is first produced in the form of a drawing and later reduced and reproduced to a solid medium. During the design of an integrated circuit, optical proximity correction (OPC) may be employed. However, with the incredible numbers of circuit elements utilized on modem integrated circuits, performing such a correction may take days.
Therefore, it would be desirable to provide a system and method for providing an optical proximity correction driven hierarchy.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an optical proximity correction driven hierarchy. In a first aspect of the present invention, a method for constructing a hierarchy of optically independent structures for use in optical proximity correction of a circuit includes receiving an integrated circuit design, the design including geometric circuit elements for providing circuit functions of an integrated circuit. At least a portion of the integrated circuit design is exploded and geometric circuit elements of the exploded integrated circuit design are gathered into optically independent classes. A search is then performed for congruency for each optically independent class.
In a second aspect of the present invention, a system for constructing a hierarchy of optically independent structures for use in optical proximity correction of a circuit includes a memory suitable for storing a program of instructions and a processor communicatively coupled to the memory. The program of instructions configures the processor to receive an integrated circuit design, the design including geometric circuit elements for providing circuit functions of an integrated circuit; explode at least a portion of the integrated circuit design; and gather geometry circuit elements of the exploded integrated circuit design into optically independent classes.
In a third aspect of the present invention, a method of performing optical proximity correction to a design of an integrated circuit includes receiving an integrated circuit design, the design including geometric circuit elements for providing circuit functions of an integrated circuit. A search is performed for congruency for at least two geometric circuit elements of the received integrated circuit design with an optically independent class arranged in a hierarchy of optically independent structures, wherein congruency is found, substituting the at least two geometric circuit elements with the optically independent structure.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5657235 (1997-08-01), Liebmann et al.
patent: 6470489 (2002-10-01), Chang et al.
Method and System for Constructing a Hierarchy-Driven Chip Covering for Optical Proximity Correction, Filed Dec. 20, 2002 10/327,314 Egorov et al.
Aleshin Stanislav V.
Egorov Evgueny E.
Medvedeva Marina
LSI Logic Corporation
Suiter - West PC LLO
Thompson A. M.
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