Optical disc player with sleep mode

Details Optical disc player with sleep mode Optical disc player with sleep mode

2000-03-03

2004-09-28

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S112000, C711S113000, C711S145000, C711S156000, C369S008000

Reexamination Certificate

active

06799242

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to an optical disc player which reads data from a recording medium, such as a compact disc (CD) or a digital video disc (DVD), and more particularly, to a reduction in the power consumption of an optical disc player in a sleep mode.
In a CD-ROM system, a digital audio CD is utilized as a read only memory (ROM) for storing digital data. A personal computer which is provided with such a CD-ROM system has a sleep mode which periodically interrupts information processing while maintaining a power on condition. The sleep mode reduces the power consumption of the computer, allowing the useful battery life for a portable personal computer, for example, to be extended.
FIG. 1
is a schematic block diagram of a conventional optical disc player
100
, which comprises a pickup
1
, a pickup control circuit
3
, an analog signal processor circuit
4
, a digital signal processor circuit
5
, a CD-ROM decoder
6
, a buffer RAM
7
and a control microcomputer
8
.
The pickup
1
irradiates a disc
2
with light to produce a voltage signal which conforms to the intensity of light reflected. The pickup control circuit
3
controls the position of the pickup
1
on the disc
2
so that the pickup
1
can read data recorded on the disc
2
in a proper sequence. A servo control which controls spin of the disc
2
at a given speed is performed with the position control of the pickup
1
, thereby assuring that a constant linear or angular velocity over tracks on the disc
2
is maintained.
The analog signal processor circuit
4
receives the voltage signal from the pickup
1
and produces an EFM (eight to fourteen modulation) signal of 588 bits in one frame.
The digital signal processor circuit
5
receives the EEM signal from the analog signal processor circuit
4
and performs EFM demodulation. The demodulated signal is subject to CIRC (Cross Interleave Reed Solomon Code) decoding, whereby 24-bytes per frame CD-ROM data is produced.
The CD-ROM decoder
6
performs a decoding operation including a read error detection and error correction on the demodulated CD-ROM data received from the digital signal processor circuit
5
, and reproduced CD-ROM data is then provided to a host computer.
The buffer RAM
7
is connected with the CD-ROM decoder
6
to temporally store the CD-ROM data supplied from the digital signal processor circuit
5
to the CD-ROM decoder
6
in units of one block. Since the error correction is performed on one block of data, the CD-ROM decoder
6
requires at least one block of CD-ROM data. In this manner, as CD-ROM data is sequentially read, one block of CD-ROM data is temporarily stored in the buffer RAM
7
. The control microcomputer
8
is a single chip microcomputer having a ROM and a RAM. A control program is stored in the ROM for controlling the CD-ROM decoder
6
. The control microcomputer
8
temporarily stores command data from the host computer or sub-code data supplied from the digital signal processor circuit
5
in its internal RAM. The control microcomputer
8
performs various control operations in accordance with commands from the host computer so that CD-ROM data is provided from the CD-ROM decoder
6
to the host computer.
Also recorded on the disc
2
is a table of contents (or TOC data) including index information which indicates what data is recorded at which position. As soon as the optical disc
2
is loaded into the optical disc player
100
, the index information is immediately read and stored in the buffer RAM
7
at a given address. Data retrieval using the TOC data allows CD-ROM data to be efficiently read from the buffer RAM
7
.
FIG. 2
is a schematic block diagram of the CD-ROM decoder
6
. The CD-ROM decoder
6
comprises an input interface
11
, a signal processor circuit
12
, a host interface
13
, a memory control circuit
14
, a microcomputer interface
15
and a switch
16
. The buffer RAM
7
is connected to the memory control circuit
14
and comprises a dynamic random access memory (DRAM).
When reading the TOC data from the disc
2
, the control microcomputer
8
causes the microcomputer interface
15
to deliver a switching signal SW, which moves the switch
16
to enable a transfer of the TOC data to the control microcomputer
8
. The transfer of the TOC data is repeated three times to guard against a failure of the disc
2
. The control microcomputer
8
writes only one of these TOC data items to the buffer RAM
7
at a given address via the memory control circuit
14
.
The input interface
11
descrambles the CD-ROM data from the digital signal processor circuit
5
which is digitally processed and formatted, and the descrambled CD-ROM data is provided to the buffer RAM
7
via the memory control circuit
14
.
The signal processor circuit
12
reads one block of CD-ROM data stored in the buffer RAM
7
and performs an error detection and an error correction process thereon. One block of CD-ROM data includes a sync signal and an error correction code ECC, and normally comprises 2352 bytes. Erroneous data in the buffer RAM
7
is corrected under the control of the memory control circuit
14
.
The host interface
13
interfaces with the host computer, and reads CD-ROM data from the buffer RAM
7
, where it is saved, and provides it to the host computer. The host interface
13
also receives a variety of control commands from the host computer, and provides them to the control microcomputer
8
.
The memory control circuit
14
controls delivery and transfer of the CD-ROM data between the input interface
11
, the signal processor circuit
12
, and the host interface
13
on one hand and the buffer RAM
7
on the other hand. DATA entry into the input interface
11
, the error correction by the signal processor circuit
12
and data delivery from the host interface
13
are performed concurrently upon data of different blocks. An access to the buffer RAM
7
is enabled depending on the operational situations of the input interface
11
, the signal processor circuit
12
and the host interface
13
. The input interface
11
, the signal processor circuit
12
, the host interface
13
and the memory control circuit
14
operate in synchronism with a given clock signal.
Because a relatively large capacity of data is stored in the buffer RAM
7
, including a plurality of blocks of data and TOC data, it is preferred to use a DRAM. A DRAM requires a refresh operation to maintain stored data. The memory control circuit
14
controls the supply of a row address strobe (RAS) and a column address strobe (CAS) to the buffer RAM
7
in order to perform a refresh operation.
The microcomputer interface
15
receives commands from the control microcomputer
8
and distributes such commands while providing status information to the control microcomputer
8
.
A portable personal computer has a sleep mode which periodically interrupts information processing. However, it is necessary that TOC data including CD-ROM index data be stored in the buffer RAM
7
since otherwise, it is necessary to re-read the TOC data from the CD-ROM upon termination of the sleep mode, thus lengthening the data read time interval.
To maintain the TOC data stored in the buffer RAM
7
during the sleep mode, a refresh operation with a given period such as 512 cycles/8 milliseconds or 256 cycles/8 milliseconds is required. As shown in
FIG. 3
, a refresh signal generator circuit
24
uses a reference clock signal supplied from a phase locked loop (PLL) circuit
23
of a reference clock generator circuit
20
to form signals such as RAS and CAS which are used for the refresh operation, and provides these signals to the buffer RAM
7
. It will be noted that the reference clock signal is generated from the duty cycle control of the PLL circuit
23
which utilizes a reference clock produced by the combination of a crystal oscillator
21
and an inverter
22
as well as a frequency converter. Accordingly, the reference clock generator circuit
20
cannot cease its operation during the sleep mode. The reference clock signal is produced by t

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