Static information storage and retrieval – Read/write circuit – Optical
Reexamination Certificate
1999-12-17
2001-01-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Optical
C365S234000
Reexamination Certificate
active
06172926
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to optical data storage devices and methods.
DESCRIPTION OF THE RELATED ART
Background of the Invention
Dynamic random access memory (DRAM) is the principal type of memory used in most applications such as personal computers (PCs). When compared, for example, to static random access memory (SRAM), DRAM is less expensive, consumes substantially less power, and provides more bits in the same chip space (i.e. has a higher cell density). DRAM is normally used to construct those memory subsystems, such as system memories and display frame buffers, where power conservation and high cell density are more critical than speed. In most computing systems, it is these subsystems which dominate the system architecture, thus making DRAM the prevalent type of memory device on the market.
In applications where access time is critical, such as in data and instruction caches, SRAM is normally used. Notwithstanding their present speed advantage over other types of devices, the ability to fabricate SRAM cells with ever decreasing access times will eventually become limited by device physics. This limitation on speed will then have to be considered in addition to the more traditional disadvantages of using SRAMs. Among other things, since SRAM cells essentially act as latches, they continuously sink current and hence consume a significant amount of power, as already noted above. Moreover, the typical SRAM cell is constructed from multiple transistors in a cross-coupled latch arrangement, which requires more silicon area on-chip than the typical DRAM cell, which typically is constructed from a single transistor and a charge storage capacitor.
Thus, the need has arisen for new memories which are not subject to the limitations of traditional SRAMs and DRAMs. These devices, and systems embodying them, should be capable of meeting the high speed data storage requirements expected for the next generations of information processing hardware. In addition to speed, such devices should also meet the expected high storage capacity (i.e high bit density) requirements for advanced processing applications.
SUMMARY OF THE INVENTION
An optical memory is disclosed which includes an optical storage element for storing data as a packet of photons, the optical storage element delaying in time the packet of photons traveling through the storage element from a first point to a second point. A photon source receives an electrical signal representing data and injects the packet onto the optical storage element in response. A detector is provided for selectively detecting the packet traveling on the optical storage element while a feedback path couples the photon source and detector for recirculating the packet through storage element.
A data storage system is also disclosed which includes a plurality of optical storage elements and a plurality of memory control circuits for storing data as optical wave packets on corresponding ones of the plurality of storage elements. The control circuits include circuitry for converting an electrical signal into an optical wave packet and transmitting the wave packet on a corresponding one of the optical storage elements. Circuitry is also included for recirculating the wave packet on the selected optical storage element. Additionally, storage circuitry is included for detecting the wave packet on the optical storage element and recovering the electrical signal in response.
The principles of the present invention are further described in methods of storing data. According to one such method, a packet of photons is generated from an electrical signal and then transmitted on an electrical storage element having a predetermined delay between an input point of the packet and an output point of the packet. The packet is detected at the output point after the predetermined delay and the electrical signal is recovered.
The principles of the present invention allow for the construction of devices and systems which should be capable of meeting the high speed/high bit capacity data storage requirements expected for the next generations of information processing hardware. Moreover, in doing so, these principles do not require a light source of a specific frequency or that a specialized type of fiber optical filament be used, except to the extent that compatibility between the photon source, optical filament and detector must be maintained, as known in the art. Additionally, devices and systems embodying the inventive principles are essentially self-calibrating since speed can be varied as a function of the dimensions of the optical storage element. Also, devices embodying the invention have self-calibrating alignment. Advantageously, a substantial degree of freedom is allowed during the reduction of these principles to various applications.
REFERENCES:
patent: 5740117 (1998-04-01), Bona et al.
“Polarization Mode Dispersion Compensation at 20 Gb/s with Fiber-Based Distributed Equalizer” by No{acute over (e)}, Sandel, et al, 4 pages, by Universit{umlaut over (a)}t Paderborn, FB 14/850 & Siemens AG, Nov. 2, 1999.
“Wide-Band Dispersion Compensating Optical Fiber” by Goel and Shevgaonkar in 1997 p. 1-2 vol. 8, No. 12, Dec. 1996, IEEE Photonics Technology Letter.
Lam David
Murphy, Esq. James J.
Nelms David
TelCom Semiconductor, Inc.
Winstead Sechrest & Minick
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