Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-06-22
2004-04-06
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S014000
Reexamination Certificate
active
06716683
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication, and more particularly, to techniques for optically analyzing circuitry within an integrated circuit.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
As manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
One semiconductor analysis method involves optically analyzing integrated circuits in silicon using, for example, microscope-based analysis, picosecond imaging circuit analysis (PICA), and electro-optic probing. Optical analysis of integrated circuits having silicon on insulator (SOI) structure, however, has been challenging. In particular, it has been difficult to detect photoemissions in the visible light range (e.g., visible to near infrared (nIR), or between about 500 nanometers and 1.5 microns) through the insulator of the SOI structure. In addition, die surface preparations used prior to analyzing SOI circuit structure can vary, and the variance affects the ability to optically analyze the circuitry.
SUMMARY OF THE INVENTION
The present invention is directed to approaches for addressing challenges discussed above, including challenges to optical analysis of semiconductor dies having SOI structure, as exemplified in a number of implementations and applications, some example aspects of which are summarized below.
According to an example embodiment of the present invention, an integrated circuit die having silicon on insulator (SOI) structure is analyzed using lens optimization for the detection of photons from the die. An integrated circuit die having at least a portion of the insulator of the SOI structure exposed is stimulated. Visible photon emissions (photoemissions) from the die are detected through the insulator of the SOI with first and second different lenses. The photoemissions detected using the first and second lenses are compared and the one of the first and second lenses that has a higher photon count rate is identified. The lens having a higher photon count rate is then used to detect photoemissions from the die, and the detected photoemissions are used in the analysis of the die. In this manner, optical analysis including photon detection from dies having SOI structure is achieved, and the lens used for the optical analysis is adapted for the particular die preparation used.
In a more particular example embodiment of the present invention, two lenses are used to analyze the die. A photoemission detection lens is identified using the above method, and a second lens is selected for imaging the die with high resolution. The second lens is used to identify a circuit element in the die for analysis, and the first lens is then used to detect photoemissions from the identified circuit element. In this manner, the photoemission detection lens can be optimized for detection of photons, and the circuit identification lens can be optimized for imaging the die. In one implementation, the two-lens analysis is accomplished in a single detection arrangement adapted to use both lenses.
In another example embodiment of the present invention, a system is adapted for the detection of photons from an integrated circuit die having SOI structure. The system includes a substrate removal arrangement adapted to provide an integrated circuit die having at least a portion of the insulator of the SOI structure exposed. A die analysis tool is adapted to stimulate the integrated circuit die in a manner that generates photoemissions. A detector is used to detect the photoemissions from the die via the insulator of the SOI structure with a first lens and another detector is used to detect photon emissions from the die via the insulator with a second lens that is different from the first lens. A comparison arrangement is adapted to compare the photon emissions detected using the first and second lenses and to identify which of the first and second lenses has a higher photon count rate. Once the lens having the higher photon count rate is identified, a detector is adapted to use the identified lens to detect photoemissions from the die, and the detected photoemissions are used for analyzing the die.
The above summary is not intended to describe each illustrated embodiment or every implementation. The figures and detailed description that follow more particularly exemplify these embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention may be more completely understood in consideration of the following detailed description of various embodiments in connection with the accompanying drawings, in which:
FIG. 1
is a flow diagram for analyzing an integrated circuit die, according to an example embodiment of the present invention;
FIG. 2
is a system adapted to analyze an integrated circuit die, according to another example embodiment of the present invention; and
FIG. 3
is graph showing photon emission counts, used in connection with another example embodiment of the present invention.
REFERENCES:
patent: 4755874 (1988-07-01), Esrig et al.
patent: 5061850 (1991-10-01), Kelly et al.
patent: 5301006 (1994-04-01), Bruce
patent: 5391885 (1995-02-01), Imataki et al.
patent: 5661520 (1997-08-01), Bruce
patent: 5754291 (1998-05-01), Kain
patent: 5940545 (1999-08-01), Kash et al.
patent: 6020957 (2000-02-01), Rosengaus et al.
patent: 6031985 (2000-02-01), Yoshida
patent: 6154274 (2000-11-01), Davis et al.
patent: 6262423 (2001-07-01), Hell et al.
patent: 6262430 (2001-07-01), Li
patent: 6411377 (2002-06-01), Noguchi et al.
patent: 6462814 (2002-10-01), Lo
Inoué, Shinya, Video Microscopy, Plenum, 1986, pp. 126-127, 130-131.
Bruce Michael R.
Chin Jiann Min
Gilfeather Glen P.
Goruganthu Rama R.
McBride Shawn
Advanced Mircor Devices, Inc.
Elms Richard
Luhrs Michael
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