Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-03-03
1996-05-14
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 17, 326 97, H03K 19017
Patent
active
055171362
ABSTRACT:
An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal. Odd-numbered half-cycles begin with a domino gate of the second type controlled by the second clock signal, followed by domino gates of the first type controlled by the fourth clock signal.
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"The Metaflow Architecture", by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner, David Isaman, IEEE Micro. 1991.
Chu Ching-Hua
Harris David
Huang Sunny C.
Ilkbahar Alper
Nadir James
Hudspeth David R.
Intel Corporation
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