Operational time extension

Details Operational time extension Operational time extension

2007-06-26

2007-06-26

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S037000, C326S038000, C326S039000, C326S040000, C326S047000, C716S030000

Reexamination Certificate

active

11082200

ABSTRACT:
Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

REFERENCES:
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5521835 (1996-05-01), Trimberger
patent: 5552721 (1996-09-01), Gould
patent: 5610829 (1997-03-01), Trimberger
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5694057 (1997-12-01), Gould
patent: 5719889 (1998-02-01), Iadanza
patent: 5732246 (1998-03-01), Gould et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745422 (1998-04-01), Iadanza
patent: 5745734 (1998-04-01), Craft et al.
patent: 5764954 (1998-06-01), Fuller et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5802003 (1998-09-01), Iadanza et al.
patent: 5815726 (1998-09-01), Cliff
patent: 5889411 (1999-03-01), Chaudhary
patent: 5914616 (1999-06-01), Young et al.
patent: 5914906 (1999-06-01), Iadanza et al.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6054873 (2000-04-01), Laramie
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6075745 (2000-06-01), Gould et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6108805 (2000-08-01), Rajsuman
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6175247 (2001-01-01), Scalera et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6233191 (2001-05-01), Gould et al.
patent: 6381732 (2002-04-01), Burnham et al.
patent: 6487709 (2002-11-01), Keller et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6515509 (2003-02-01), Baxter
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6593771 (2003-07-01), Bailis et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6603330 (2003-08-01), Snyder
patent: 6629308 (2003-09-01), Baxter
patent: 6636070 (2003-10-01), Altaf
patent: 6642763 (2003-11-01), Dike
patent: 6667635 (2003-12-01), Pi et al.
patent: 6668361 (2003-12-01), Bailis et al.
patent: 6675309 (2004-01-01), Baxter
patent: 6714041 (2004-03-01), Darling et al.
patent: 6806730 (2004-10-01), Bailis et al.
patent: 6831479 (2004-12-01), Lo
patent: 6851101 (2005-02-01), Kong et al.
patent: 2002/0008541 (2002-01-01), Young et al.
patent: 2002/0113619 (2002-08-01), Wong
patent: 2002/0125910 (2002-09-01), New et al.
patent: 2002/0125914 (2002-09-01), Kim
patent: 2002/0163357 (2002-11-01), Ting
patent: 2003/0042931 (2003-03-01), Ting
patent: 2003/0080777 (2003-05-01), Baxter
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 2004/0075481 (2004-04-01), Reuveni et al.
patent: 2004/0196066 (2004-10-01), Ting
patent: 2005/0134308 (2005-06-01), Okada et al.
patent: 2006/0220716 (2006-10-01), Nicolaidis
U.S. Appl. No. 11/081,823, filed Mar. 15, 2005, Rohe.
U.S. Appl. No. 11/081,854, filed Mar. 15, 2005, Rohe.
“Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8.
“The Xilinx Virtex Series FPGA,” Jan. 22, 2001, slides 1-22.
Alpert, C.J., et al., “Quadratic Placement Revisited,” Design Automation Conference, '97, Jun. 1997, ACM.
Altera Corp., “6. DSP Blocks in Stratix II Devices,”SII52006-1.0, Feb. 2004, pp. 1-32.
Altera, “Stratix II DSP Performance,”White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, CA.
Caspi, E., et al., “A Streaming Multi-Threaded Model,”MSP-3, Dec. 2, 2001, pp. 1-23.
Caspi, E., et al., “Stream Computations Organized for Reconfigurable Executiion (SCORE): Introduction and Tutorial,” Aug. 25, 2000, pp. 1-31, Version 1.0.
Ciemat, J.V., et al., “Annealing Placement by Thermodynamic Combinatorial Optimization,”ACM Transactions on Design Automation of Electronic Systems, Jul. 2004, pp. 310-332, vol. 9, No. 3, ACM, New York, NY.
Compton, K., et al., “Reconfigurable Computing: A Survey of Systems and Software,”ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34, No. 2, ACM, New York, NY.
Cong, J., et al., “Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays,”ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1, No. 2, ACM, Inc.
Cong, J., et al., “Large-Scale Circuit Placement,” ACM Transactions on Design Automation of Electronic Systems, Apr. 2005, pp. 389-430, vol. 10, No. 2, ACM Inc., Broadway, New York, NY.
Davare, A., et al., “The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications,”DAC '04, Jun. 7-11, 2004, ACM, San Diego, California, USA.
Dehon, A., Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization). pp. 1-10. (Applicants believe that this article also appears inProceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-134.).
Dehon, A., “Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density,”Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, May 1996, pp. 47-54.
Dehon, A., “Reconfigurable Architectures for General-Purpose Computing,”A.I. Technical Report No. 1586, Oct. 1996, pp. i-353.
Dehon, A., “The Density Advantage of Configurable Computing,” Apr. 2000, pp. 41-49, IEEE.
Dehon, A., “Transit Note #121: Notes on Programmable Interconnect,”M.I.T. Transit Project, Feb. 1995, pp. 1-13.
Dehon, A., et al., “Design Patterns for Reconfigurable Computing,”Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Apr. 2004.
Dehon, A., et al., “DPGA-Coupled Microprocessors: Commodity ICs for the Early 21stCentury,”FCCM '94-IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 10-13, 1994.
Gayasen, A., et al., “Reducing Leakage Energy in FPGAs Using Region-Constrained Placement,”FPGA '04, Feb. 22-24, 2004, pp. 51-58, ACM, Monterey, California, USA.
George, V., “Low Energy Field-Programmable Gate Array,”A Dissertation Submitted in Partial Satisfaction o the Requirements for the Degree of Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley, Fall 2000, pp. 1-190, no month.
Heidari, G., et al., “Introducing a Paradigm Shift in the Design and Implementation of Wireless Devices,”A Wireless Devices Whitepaper, Apr. 28, 2004 but © 2003, pp. 1-10, QuickSilver Technology, Inc., San Jose, California.
Hofstee, H.P., “Cell Broadband Engine Architecture from 20,000 Feet,” Aug. 24, 2005, pp. 1-6.
Huang, A.S., “Tao: An Architecturally Balanced Reconfigurable Hardware Processor,”Submitted to the Dept. of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degrees of Bachelor of Science in Electrical Science and Engineering and Master of Engineering in Electrical Engineering and Computer Science at the Massachusetts Institute of Tech

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