Operational circuit

Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing

Reexamination Certificate

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C710S024000, C710S026000

Reexamination Certificate

active

07853733

ABSTRACT:
An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

REFERENCES:
patent: 6327615 (2001-12-01), Kasper
patent: 6816921 (2004-11-01), Jahnke et al.
patent: 7177988 (2007-02-01), Efland et al.
patent: 2005/0060441 (2005-03-01), Schmisseur
patent: 2006/0080479 (2006-04-01), Anjo et al.
patent: 2007/0073922 (2007-03-01), Go et al.
patent: 06-259268 (1994-09-01), None
Rosenberg et al. “An RTP Payload Format for Generic Forward Error Correction”, RFC2733, Dec. 1999.

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