Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2002-11-29
2004-02-24
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06697994
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operation processing apparatus incorporated into a mobile communication apparatus and an operation processing method, and particularly one that realizes effective processing of a convolutional encoder and a turbo encoder thereof.
2. Description of the Related Art
In recent years, a digital signal processor (hereinafter referred to as DSP) is frequently used as type of processor embedded into an apparatus such as a cellular phone, etc. in accordance with movement toward digitalization in the field of the mobile communications. In data communications through a mobile radio communication network, since a bit error frequently occurs, error correction processing must be preformed. As one of error correcting methods, there is convolutional code processing, and DSP is used to execute convolutional code processing.
The following will explain conventional code processing briefly.
A convolutional code is produced by modulo 2-adder of an input bit and a preceding constant bit, and a plurality of code data in produced in accordance with input of one bit. When code data of n bits is produced with respect to the input of one information bit, a coding rate results in 1
. A constraint length K, which is the number of input information bits exerting an influence upon code data of an output, is equal to the number of stages of shift registers used in modulo 2-adder.
This code data is fixed by the input bit and the state of preceding (K−1) input bits. Therefore, a predefined number of bits, which are selected from data of K bits, are used as an operation target and all selected bits are EXCLUSIVE ORed, whereby convolutional processing is executed.
An operation processing apparatus for carrying out this convolutional processing at high speed is disclosed in Unexamined Japanese Patent Publication No. Hei
6-44051.
This apparatus comprises a data register for storing operation target data, a bit selection circuit for designating a configuration bit of operation target data output from the data register for each bit and for outputting bit selection data, and a multi-input exclusive OR circuit for executing EXCLUSIVE OR operations with respect to all bits of bit selection data output from this bit selection circuit, simultaneously.
In the multi-input exclusive OR circuit, the simultaneous execution of the exclusive OR operations makes it possible to carry out the selection of the operation target bit in convolutional code processing and the exclusive OR operations at high speed.
However, since the above-mentioned conventional operation processing apparatus realizes data update processing of K bits severing as an operation target by use of software, it is necessary to provide processing in which data stored in the shift register is read, shifted by a shift operating unit, etc. and written back to the resister. In this series of processing, since more than ten steps per one bit are needed, the above-mentioned operation processing apparatus is still not good enough in view of the high speed performance of the entirety of convolutional code processing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an operation processing apparatus, which is capable of efficiently performing convolutional code processing and turbo code processing at high speed and to provide an operation processing method.
This object can be achieved by comprising a data register as a first shift register, and a second register for shift inputting uncoded data to the first shift register, and executing exclusive OR operations with respect to all bit data selected from data stored in the first shift register, simultaneously.
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English Language Abstract of JP-6-44051.
English Language Abstract of JP-11-46148.
Baker Stephen M.
Greenblum & Bernstein P.L.C.
Matsushita Electric - Industrial Co., Ltd.
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