Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-01-14
2003-04-29
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233500, C365S233100, C365S189011
Reexamination Certificate
active
06556498
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operation method of an SRAM (Static Random Access Memory) device. More particularly, the present invention relates to an operation of a SRAM, which can efficiently perform read/write accessing operations and refresh operation for such SRAM device.
2. Description of the Related Art
Some conventional semiconductor memories, such as dynamic random access memory (DRAM), must be periodically refreshed in order to retain valid data. During refresh operations, external accessing data typically is not allowed. In addition, a mechanism is required to inform the memory controller that the DRAM is performing a refresh operation. Any pending memory transaction has to be delayed until the refresh operation is completed. Refresh operations therefore lengthen the overall access time for memory accesses. It is therefore important to design a memory system in which the impact of refresh operations on external memory access is minimized.
SUMMARY OF THE INVENTION
The present invention provides an operation method for a SRAM device which can statically maintains valid data with a benefit that refresh operations required by the 1-T SRAM do not interfere with any external access of the 1-T SRAM under any situation.
To achieve the objective mentioned above, the present invention provides an operation method for a static random access memory (SRAM) device. The SRAM device has a plurality of memory cells, each of the memory cells is periodically refreshed to retain valid data. The operation method comprising steps of receiving an access address and a refresh address for the SRAM device and detecting whether a transition pulse and a refresh pulse being generated. The access address is used for accessing data stored in the SRAM device and the refresh address is used for periodically refreshing the memory cell in the SRAM. The transition pulse is generated by an address transition detector when a read/write operation is issued. The refresh pulse is generated in response to a refresh clock being in an active state. If the transition pulse is generated before the refresh pulse being generated within a first time period, the access address is used to access data stored in the SRAM device at the time of the rising edge of the transition pulse. The refresh address is used to refresh the memory cell of the SRAM device in accordance with the refresh address at least the first period later after the rising edge of the transition pulse being issued. The first time period is a time period sufficient enough to accomplish the read/write operation.
If the refresh pulse is generated before the transition pulse is generated within a second time period, the refresh address is used to refresh the memory cells of the SRAM device in accordance with the refresh address at the time of the rising edge of the refresh pulse. The access address is used to access data stored in the memory cell of the SRAM device in accordance with the access address at least the second period later after the rising edge of the refresh pulse being issued. The second time period is a time period sufficient enough to accomplish the refresh operation.
In the above-described operation method of a SRAM device, in the step of detecting whether the transition pulse and the refresh pulse being generated, if the transition pulse is generated before the refresh pulse being generated larger than the first time period, the access address is used to access data stored in the SRAM device at the time of the rising edge of the transition pulse, the refresh address is used to refresh the memory cell of the SRAM device in accordance with the refresh address after the read/write operation being accomplished.
In the above-described operation method of a SRAM device, in the step of detecting whether the transition pulse and the refresh pulse being generated, if the refresh pulse is generated before the transition pulse is generated larger than the second time period, the refresh address is used to refresh the memory cells of the SRAM device in accordance with the refresh address at the time of the rising edge of the refresh pulse. The access address is used to access data stored in the memory cell of the SRAM device in accordance with the access address after the refresh operation being accomplished.
To achieve the objective mentioned above, the present invention provides an operation method of a static random access memory (SRAM) device. The SRAM device has a plurality of memory cells, each of the memory cells is periodically refreshed to retain valid data. The operation method comprising steps of receiving an access address and a refresh address for the SRAM device and detecting whether a transition pulse and a refresh pulse being generated. The access address is used for accessing data stored in the SRAM device and the refresh address is used for periodically refreshing the memory cell in the SRAM. The transition pulse is generated in response to a read/write operation being issued, and the refresh pulse is generated in response to a refresh clock being transited to an active state.
If the transition pulse is generated before the refresh pulse being generated, the access address is used to access data stored in the SRAM device at the time of the rising edge of the transition pulse. The refresh address is used to refresh the memory cell of the SRAM device in accordance with the refresh address after the read/write operation being accomplished.
If the refresh pulse is generated before the transition pulse being generated, the refresh address is used to refresh the memory cells of the SRAM device in accordance with the refresh address at the time of the rising edge of the refresh pulse, the access address is used to access data stored in the memory cell of the SRAM device in accordance with the access address after the refresh operation being accomplished.
In the above-described operation method of a SRAM device, in the step of detecting whether the transition pulse and the refresh pulse being generated, if the transition pulse is generated before the refresh pulse being generated larger than the first time period, the access address is used to access data stored in the SRAM device at the time of the rising edge of the transition pulse, the refresh address is used to refresh the memory cell of the SRAM device in accordance with the refresh address after the read/write operation being accomplished.
In the above-described operation method of a SRAM device, in the step of detecting whether the transition pulse and the refresh pulse being generated, if the refresh pulse is generated before the transition pulse is generated larger than the second time period, the refresh address is used to refresh the memory cells of the SRAM device in accordance with the refresh address at the time of the rising edge of the refresh pulse. The access address is used to access data stored in the memory cell of the SRAM device in accordance with the access address after the refresh operation being accomplished.
To achieve the objective mentioned above, the present invention provides an operation method of a static random access memory (SRAM) device. The SRAM device has a plurality of memory cells, each of the memory cells is periodically refreshed to retain valid data. The operation method comprising receiving an access address, a refresh address and a chip deselected signal for the SRAM device and detecting the chip deselected signal being in an active state and detecting whether a transition pulse and a refresh pulse being generated. The access address is used for accessing data stored in the SRAM device and the refresh address is used for periodically refreshing the memory cell in the SRAM device. The chip deselected signal is used to indicate the SRAM device being selected for data processing. The transition pulse is generated in response to a read/write operation being issued. The refresh pulse is generated in response to a refresh clock being transited to an active state.
If the deselected signal
J. C. Patents
Lam David
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