Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1998-03-27
2001-02-27
Lee, Thomas C. (Department: 2787)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C710S120000
Reexamination Certificate
active
06195758
ABSTRACT:
TECHNICAL FIELD
The present invention relates to distribution of a clock signal having redundancy to a user of the signal and in particular methods and devices for maintenance of circuits for distribution and of circuits for selecting a suitable clock signal. It also relates to networks or installations having maintenance functions provided therein. Further, it relates to a method and a clock source for providing a clock signal having identification information contained or hidden therein. It relates also to a method and a device for processing a clock signal to detect information contained therein. It relates to a method and a clock source for providing a clock signal having intentional errors contained therein. It relates to a method and a device for processing a clock signal in order to determine errors, in particular frequency and phase errors, in a clock signal. Further, the invention also relates to supplying redundant clock signals to cascaded subsystems, i.e. subsystems connected to each other serially, the clock signal passing through one subsystem where it is processed and then issued as a new clock signal to a following subsystem, etc. It further relates to methods and devices for evaluating two clock signals as to the timing of timing pulses in the clock signals in relation to each other. The invention relates also to a method and a device for producing a pulse indicating a signal sequence detected inside a clock signal. Finally, it relates to a method and a device for detecting a signal sequence contained or hidden in a clock signal.
BACKGROUND
In the field of telephone connections and in telecommunication equipment generally, as a rule there exists a need for distribution of two clocking signals, herein called clock and synchronizing pulse rates, the latter one called “synch rate” in short, to various sub
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equipments and components therein. This distribution is particularly wide in physically large connected systems, such as in the type of switches having various multiplexing stages and similar units. The clock rate has generally a high frequency and among other things defines borders for bits in the data flowing through the equipment and the synch rate has a low frequency and defines frame borders and similar things in the data signal. The number of signals transferring clock and synch information in an equipment such as a telecommunication switch station can be rather large and in the following the general expression “the clock distribution network” is used therefor. Telecommunication equipment in a magazine or cabinet, etc., has a considerable multitude of transmission components for rate distribution in the shape of cables, pins in back planes and electrical terminals, lines in back planes, etc. The space required for all such signal connections is considerable and costs money. As a rule, the number of pins in a connector is a small resource limiting the size of for example a switch.
In equipments having large requirements of their reliability the clock distribution network must of course also fulfil large reliability requirements. The reliability of the clock distribution network can be enhanced, in the conventional way, by introducing redundancy. If the clock distribution and the clock source are designed to include redundancy, i.e. that they may be duplicated or, as is supposed in the following herein, in the preferred case triplicated, a redundant and triplicated clocking structure can be maintained from clocking source to clocking receiver, however, in the receiver end one of the clocks must of course be selected for operational use by the respective equipment.
In previous systems not having redundancy, where clock rate and synch rate are to be distributed to all magazines and cabinets, as a rule two coaxial cable have been used to each receiver or user of the rates, one coaxial cable for the high frequent clock rate and one cable for the low frequency reference rate, that we call also the frame rate or the synch rate herein.
For distribution of clocking rates, where the high frequency clock is distributed separated from the low frequency synch rate, the precision must be great so that for example the pulses in the synch rate will not end up or be interpreted at the wrong one of the edges of the clock rate pulses. This poses among other things great requirements on the similarity of the lengths of the two cables used for clock and synch rate, respectively, in relation to each other and also in relation to other pairs of cables having other destinations in the system.
Distribution of a clock signal which has a very high frequency and by means of which circuits in telecommunication systems presently generally operate, in addition poses large requirements on the shielding of cables and connectors, etc. together with good grounding connections and similar things, so that interference protection and functionality can be provided and also maintained during a long time.
In for example large switches having circuits on circuit boards in magazines and cabinets there is thus a need for distributing a clock having a relatively high frequency and a rate having a lower frequency as a reference for frame structures, etc. Clock rate and synch rate can be distributed in the shape of a single, composite signal (“Composite Clock Signal”), herein called CLSY (CLock and SYnch), as described in the International Patent Application PCT/SE94/00321, which is incorporated herein by reference.
This signal comprises a clock frequency or clock rate that has a frequency considerably lower than the real system frequency at which the circuits of the system operate, i.e. is advantageously an even fraction thereof such as {fraction (1/36)} thereof, and it further comprises a synch frequency or synch rate that is modulated on top of this clock frequency and advantageously is an even fraction, such as {fraction (1/640)}, thereof.
A phase-locked loop circuit, PLL, is provided with logic circuits interpreting the synch information in the composite CLSY signal and it also generates a clock signal having a frequency that is considerably higher than the clock frequency of the CLSY signal, such as for example in a similar way as above, 36 times thereof. The PLL issues the synch pulse with a precision in relation to the system clock that would have been very difficult to produce using conventional clock distribution on two separate lines.
The advantages of distributing a frequency in the shape of CLSY, that has a considerably lower frequency compared to the system clock and in addition is provided with synch information and of arranging for a PLL to generate the system clock rate together with synch rate are:
1. The signal can be distributed more easily from an EMC point of view, i.e. in regard of sensitivity to interference from the outside and in regard of its own interfering influence. The distribution medium must not have the same precision as in the case where system clock and synch rate would have been distributed separately. This implies that for instance a single optocable can be used.
2. Pins and space in connectors and back planes, etc. are saved by using the same physical signal paths for both clock rate and synch rate.
3. A very good precision can be achieved by the arrangement that the PLL generates both the system clock and the synch on the same chip and from the same signal.
Redundant clock distribution systems are disclosed in the documents discussed briefly hereinafter and also in other documents.
In the Japanese Patent Application JP-A 60-225982 clock pulse synchronization is described in a triplicated system. A harmful influence of errors is prevented by correction by means of majority decisions.
In U.S. Pat. No. 4,185,245 an arrangement is described for fault-tolerant clock signal distribution. First and second redundant clock signal sources are arranged. Clock receivers include sequential logic circuits for examining the two clock signals in order to ignore the clock signal pulse train that comes after the other one as to the phases thereof.
U.S. Pat. No. 4,489,412 discl
Bjenne Anders
Lundh Peter
Wilhelmsson Mats
Burns Doane Swecker & Mathis L.L.P.
Lee Thomas C.
Patel Nitin
Telefonaktiebolaget LM Ericsson
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