Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2006-03-28
2006-03-28
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S500000, C340S870030, C370S235000
Reexamination Certificate
active
07020795
ABSTRACT:
The present invention provides an operating method for detecting and solving the underflow and the overflow by using the oversampling. The operating method is suitable for the transmitter and the receiver that are using different clock frequencies to transmit data. In the present operating method, when the receiver receives a plurality of received packages, the leading edge sampling phase of each received package having the most frequency in the first synchronous period is used as the initial leading edge sampling phase. Afterwards, the underflow circulation center point and overflow circulation center point are determined. Then, the underflow operation and the overflow operation are processed according to the underflow circulation center point and overflow circulation center point. The extra bit is thrown away when the underflow operation is processing, and the lost bit is inserted when the overflow operation is processing.
REFERENCES:
patent: 5699389 (1997-12-01), Beladi et al.
patent: 6477181 (2002-11-01), Fujimori et al.
patent: 6631429 (2003-10-01), Cota-Robles et al.
patent: 1009125 (2000-06-01), None
Chu Yu-Chin
Wang Yi-Tang
Yung Chih-Wen
Browne Lynne H.
Faraday Technology Corp.
Stoynov Stefan
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