Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-16
2003-08-05
Le, Vu A. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000
Reexamination Certificate
active
06603175
ABSTRACT:
Japanese patent application No. 2000-302647, filed on Oct. 2, 2000, is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to a semiconductor integrated circuit that comprises a field-effect transistor of a silicon-on-insulator (SOI) structure, together with a timepiece and electronic equipment provided with the same.
2. Background
Recent advances in integration techniques and communications technology have led to the spread of more portable electronic equipment such as cellphones and data terminals, and there is demand for even lower power consumptions of the semiconductor integrated circuits incorporated therein.
For example, a recent trend has been an increase in wristwatches that do not use a primary battery, from environmental considerations, but instead charge a secondary battery by self-generated power obtained by self-winding, a solar cell, or the thermoelectric effect, to act as a power source for a motor and an internal control IC. Another recent trend is the implementation of a watch in which hands are driven mechanically by a mainspring and, at the same time, power is generated for a quartz oscillator or internal control IC, guaranteeing timekeeping that is as accurate as a quartz timepiece. In such a case, the upper limits on the operation voltage and operation current that are permitted for the internal control IC are 0.5 volts (V) and 50 nano-amperes (nA), by way of example.
In general, this control IC is configured of metal-oxide semiconductor (hereinafter abbreviated to MOS) transistors. To reduce the power consumption of such a control IC, it is obvious to reduce the parasitic capacitances of the MOS transistors therein, but the most effective method is to reduce the operation voltage, because the power consumption is proportional to the square of the operation voltage (power voltage).
Devices of a silicon-on-insulator (SOI) construction are characterized in that, if the junction capacitance is reduced, it becomes possible to reduce the operation voltage by using a lower threshold voltage. They are therefore attracting attention as a technique of implementing circuits that are required to operate at extremely low power consumptions, as mentioned above.
In such an SOI MOS field-effect transistor (hereinafter abbreviated to FET), a body region is formed from a silicon layer in the region corresponding to the channel region of a bulk-structure MOSFET. The behavior and characteristics of this transistor depend on whether or not there is a neutral region in which there are carriers moving between the source region and the drain region.
Such transistors can be divided into two types: ones in which there is a neutral region within the body region, which are called partially depleted (PD), and ones in which there is no neutral region, called fully depleted (FD). The presence of this neutral region depends on the thickness of the silicon layer that forms the body region.
A fully-depleted SOI MOSFET has excellent saturation characteristics and has the advantage that it can be applied to reduced power consumptions. However, there is a disadvantage in that the techniques of fabricating the requisite thin silicon layer are difficult and thus it is not possible to achieve accurate threshold voltage control.
In contrast thereto, a partially-depleted SOI MOSFET has advantages in that it has a fabrication margin due to the thickness of the silicon layer of the body region, and also the same bulk-orientated processing can be used to fabricate it. However, it has a disadvantage in that, when the body region is in a floating state, the substrate floating effect caused by the carriers within the neutral region leads to instability, and also a kink is generated by the parasitic bipolar operation.
Simply using fully-depleted SOI MOSFETs in the fabrication of a semiconductor integrated circuit designed to operate at an ultra-low power consumption, such as a wristwatch IC, causes problems in that threshold voltage control becomes difficult because of the thinness of the silicon layer, and also the increased fabrication costs make it difficult to mass-produce it. Simply using partially-depleted SOI MOSFETs in the fabrication of the semiconductor integrated circuit, on the other hand, means that operation at extremely low power consumptions is not possible because of instability caused by factors such as the abovementioned substrate floating effect.
SUMMARY
According to one aspect of the present embodiment, there is provided a semiconductor integrated circuit comprising: a first power line which supplies a first voltage potential;
a second power line which supplies a second voltage potential that is lower than the first voltage potential;
a voltage regulator circuit connected electrically to the first and second power lines;
a third power line which supplies a voltage generated by the voltage regulator circuit, with reference to the first voltage potential; and
an operating circuit connected electrically to the first and third power lines;
wherein at least one transistor among transistors comprising the voltage regulator circuit is a partially-depleted SOI field-effect transistor in which a body region and a source region are connected electrically; and
wherein at least one transistor among transistors comprising the operating circuit is a partially-depleted SOI field-effect transistor in which the body region is in an electrically floating state.
According to another aspect of the present embodiment, there is provided a semiconductor integrated circuit comprising: a first power line which supplies a first voltage potential;
a second power line which supplies a second voltage potential that is lower than the first voltage potential;
a first circuit connected electrically to the first and second power lines;
a third power line which supplies a constant voltage generated by the first circuit with reference to the first voltage potential; and
a second circuit connected electrically to the first and third power lines,
wherein at least one transistor among transistors comprising the first circuit is a partially-depleted SOI field-effect transistor in which a body region and a source region are connected electrically; and
wherein at least one transistor among transistors comprising the second circuit is a partially-depleted SOI field-effect transistor in which the body region is in an electrically floating state.
According to a further aspect of the present embodiment, there is provided a semiconductor integrated circuit comprising:
a digital circuit section;
an analog circuit section;
wherein the digital circuit section comprises a plurality of field-effect transistors and at least one transistor is a partially-depleted SOI field-effect transistor in which a body region is in an electrically floating state; and
wherein the analog circuit section comprises a plurality of field-effect transistors and at least one transistor is a partially-depleted SOI field-effect transistor in which a body region and a source region are connected electrically.
REFERENCES:
patent: 5818781 (1998-10-01), Estakhri et al.
patent: 6087893 (2000-07-01), Oowaki et al.
patent: 6160292 (2000-12-01), Flaker et al.
patent: 2001/0045602 (2001-11-01), Maeda et al.
Ebina Akihiko
Kadowaki Tadao
Sato Yoko
Yamaguchi Masayuki
Le Vu A.
Oliff & Berridge PLC.
Seiko Epson Corporation
Smith Brad
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