Operating array cells with matched reference cells

Details Operating array cells with matched reference cells Operating array cells with matched reference cells

2006-10-17

2006-10-17

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185030

Reexamination Certificate

active

07123532

ABSTRACT:
A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

REFERENCES:
patent: 6396741 (2002-05-01), Bloom et al.
patent: 6490204 (2002-12-01), Bloom et al.
patent: 2004/0257873 (2004-12-01), Shieh et al.

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