Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-12-17
1999-10-05
Lee, Thomas C.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 37, 714 39, G06F 1130
Patent
active
059616547
ABSTRACT:
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
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Performance Monitor, PowerPC 604 RISC Microprocessor User's Manual, Chapter 9, pp. 9-1 through 9-11, IBM 1994.
Levine Frank Eliot
Moore Roy Stuart
Roth Charles Philip
Welbon Edward Hugh
Davis Jr. Walter D.
International Business Machines - Corporation
Kordzik Kelly K.
Lee Thomas C.
McBurney Mark E.
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