Operable floating gate contact for SOI with high Vt well

Details Operable floating gate contact for SOI with high Vt well Operable floating gate contact for SOI with high Vt well

1998-10-20

2001-06-19

Abraham, Fetsum (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S374000, C257S375000, C257S376000, C257S347000, C257S551000, C257S491000, C257S501000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000

Reexamination Certificate

active

06249028

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices. In particular, the present invention relates to semiconductor-on-insulator (SOI) devices. More particularly, present invention relates to a floating gate protect diode structure for SOI devices.
BACKGROUND OF THE INVENTION
Semiconductor-on-insulator (SOI) technology relates to high-speed MOS and CMOS circuits. According to SOI, a thin layer of semiconductor material is deposited on an insulator to reduce the capacitive coupling between the semiconductor layer and the underlying substrate material.
CMOS FET gates are subjected to charging that can degrade gate insulator quality. Typically, circuits on a semiconductor chip include at least one protective component. A common solution in bulk CMOS is to connect a diode between the FET gate and the FET body at the first wiring, or metal, level available. This is the floating-gate protect diode (FGPD). The FGPD is electrically isolated from the FET source and drain and require a small area, for example, a single contact, in bulk CMOS.
Charge accumulated in the FET gate during subsequent processing will discharge through the FGPD into the FET body and not through the FET insulator. Thus, damage to the insulator is avoided.
However, inherent to silicon-on-insulator (SOI) structures is the inability to form dense diodes between the FET gate and body that are electrically isolated from the FET source and drain.
SUMMARY OF THE INVENTION
The present invention provides solutions to these and other problems by presenting an FET structure for utilization with a silicon-on-insulator semiconductor device structure. The structure includes a silicon-on-insulator substrate structure. Source and drain diffusion regions are provided on the silicon-on-insulator substrate. An FET body region is interconnected with the source and drain diffusion regions. A gate oxide region is arranged over at least a portion of the body region and the source and drain diffusion regions. A gate region is arranged over at least a portion of the gate oxide region. A diode is interconnected with and provides a conductive pathway between the gate region and the FET body region. The diode is electrically isolated from the FET source and drain regions and inversion channel by a high threshold FET region.
Aspects of the present invention also provide methods for forming an FET structure including a diode on a silicon-on-insulator semiconductor structure.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.


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