Open-drain fet output circuit

Details Open-drain fet output circuit Open-drain fet output circuit

1995-05-24

1997-01-14

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 86, 326121, H03K 190175

Patent

active

055943691

ABSTRACT:
An input signal is inverted by an inverter in the first stage and an n-channel MOS transistor on the pull up side in a driver is driven, while an output signal of the inverter in the first stage is inverted by an inverter in the next stage and an n-channel MOS transistor on the pull down side is driven. A driving signal is output from a connection point between the n-channel MOS transistor on the pull up side and the n-channel MOS transistor on the pull down side, and an output transistor is driven by the driving signal. Since a gate voltage of the output transistor increases only by a value of a power supply voltage Vdd minus threshold voltage V.sub.T, a rise time and a fall time of a gate potential can be reduced, resulting in improvement in the duty cycle.

REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5043604 (1991-08-01), Komaki
patent: 5122691 (1992-06-01), Balakrishnan
patent: 5408146 (1995-04-01), Nguyen
patent: 5414375 (1995-05-01), Tsuboi

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