Electronic digital logic circuitry – Tri-state – With field-effect transistor
Reexamination Certificate
2002-01-22
2003-06-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Tri-state
With field-effect transistor
C326S056000, C326S058000, C326S030000
Reexamination Certificate
active
06580290
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to integrated circuit devices, and more particularly to an output driver circuit of an integrated circuit device for high speed communication.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) devices for high speed communication, such as fiber optics networking IC devices and other networking IC devices, include output driver circuits to drive downstream external devices using logic signals. However, the input circuits of these downstream external devices may be designed with different specifications. As an example, some input circuits may be designed to be compatible to open collector/drain specifications, while other input circuits may be designed to be compatible to stub series-terminated logic (SSTL) specifications. Consequently, there are different designs of output driver circuits so that the output driver circuits can properly function with the particular input circuits of the downstream external devices.
In
FIG. 1
, a simple exemplary output driver circuit
100
that is compliant to open collector/drain specifications is shown. The output driver circuit includes a pull down device
102
, which in this example is a metal oxide semiconductor (MOS) transistor. However, the pull-down device can be a different active device, such as a bipolar transistor. The pull-down MOS transistor is connected between an output terminal
104
and ground. The gate of the pull-down MOS transistor is connected to an input terminal
106
to receive high and low input signals, which represent logical signals of 1's″ and 0's. When a high input signal (i.e., a logical signal of 1) is applied to the input terminal, the pull-down MOS transistor is activated, and thus, the output terminal is grounded. In contrast, when a low input signal (i.e., a logical signal of 0) is applied to the input terminal, the pull-down MOS transistor is deactivated, and thus, the output terminal is floated.
These two conditions on the output terminal
104
of the output driver circuit
100
to provide high and low states on the input terminal of a downstream external device (not shown). When the output terminal of the output driver circuit is grounded, the voltage on the input terminal of the downstream external device is pulled down to produce a low signal (i.e., a logical signal of 0). Thus, when a high input signal is applied to the input terminal
106
of the output driver, a low signal is produced on the input terminal of the downstream external device. However, when the output terminal of the output driver circuit is floated, the voltage on the input terminal of the downstream external device is pulled up using a resistor connected to a voltage source of the external device to produce a high signal (i.e., a logical signal of 1). Thus, when a low input signal is applied to the input terminal of the output driver, a high signal is produced on the input terminal of the downstream external device.
In
FIG. 2
, a simple exemplary output driver circuit
200
that is compliant to SSTL specifications is shown. The output driver circuit includes a pull-down device
202
and a pull-up device
204
. In this example, the pull-down device is an N-channel MOS transistor and the pull-up device is a P-channel MOS transistor. However, similar to the output driver circuit
100
of
FIG. 1
, other types of active devices may be used for the pull-down and pull-up devices. The PMOS transistor is connected between a supply voltage source V
cc
and an output terminal
206
, while the NMOS transistor is connected between the output terminal and ground. The gates of the MOS transistors are connected to an input terminal
208
to receive high and low input signals, which again represent logical signals of 1's″ and 0's. When a high input signal (i.e., a logical signal of 1) is applied to the input terminal
208
, only the pull-down NMOS transistor is activated, and thus, the voltage on the output terminal
206
is pulled low to provide a low output signal. In contrast, when a low input signal (i.e., a logical signal of 0) is applied to the input terminal, only the pull-up PMOS transistor is activated, and thus, the voltage on the output terminal is pulled up to provide a high output signal. Thus, the output driver circuit
200
provides inverted low and high output signals in response to high and low input signals.
The compatibility of an output driver circuit of an IC device with the input circuit of a downstream external device depends on the specifications of both circuits. However, the specification of the input circuit is often unknown to the designer of the IC device. Thus, different designs of the output driver circuit need to be constructed to ensure that the IC device will be compatible to various input circuits of the downstream external devices. Otherwise, the IC device may not work with a particular input circuit of the downstream external device.
In view of this concern, there is a need for an output driver circuit that is compliant with both open collector/drain and SSTL specifications and a method for operating the output driver circuit.
SUMMARY OF THE INVENTION
An output driver circuit that is compliant to both open collector/drain and stub series-terminated logic (SSTL) specifications and a method of operating the output driver circuit utilize a feedback loop to monitor the voltage on the output terminal of the output driver circuit to selectively deactivate either a pull-up or pull-down device. The use of the feedback loop allows the output driver circuit to float the output terminal when the voltage on the output terminal has exceeded or fallen below a threshold voltage. Consequently, the output driver circuit can provide output signals that are compatible to SSTL specifications by selectively activating one of the pull-up and pull-down devices, or signals that are compatible open collector/drain specifications by selectively deactivating both pull-up and pull-down devices to float the output terminal.
An output driver circuit in accordance with the present invention includes a pull-up device, a pull-down device and a feedback loop. The pull-up device is connected between a high voltage terminal and an output node, while the pull-down device is connected between the output node and a low voltage terminal. The pull-up and pull-down devices are configured to produce an output signal on the output node in response to an input signal. The pull-up and pull-down devices may be metal oxide semiconductor (MOS) transistors, bipolar junction transistors (BJTs), high electron mobility transistors (HEMTs), or any other active devices. The feedback loop is connected to the output node and either the pull-up or pull-down device. The feedback loop is configured to deactivate the pull-up or pull-down device when the voltage of the output signal on the output node has satisfied a predefined criterion.
In a first embodiment, the feedback loop is connected to the pull-up device to selectively deactivate the pull-up device when the voltage of the output signal on the output node has exceeded a threshold voltage. In this embodiment, the pull-down device may be connected to an input terminal of the output driver circuit such that the pull-down device is controlled by the input signal.
In the first embodiment, the feedback loop may include a differential amplifier and a pass gate. One of the inputs of the differential amplifier is connected to the output node to receive the output signal, while the other input of the differential amplifier is configured to receive a reference voltage. The output of the differential amplifier is a signal that is proportional to the voltage difference between the output signal and the reference voltage. The pass gate is connected to the output of the differential amplifier and the pull-up device. The pass gate is configured to transmit the signal from the differential amplifier to the pull-up device when the pass gate is enabled. The pass gate may be configured to be enabled when the input signal is a particular type of si
Agilent Technologie,s Inc.
Tokar Michael
Tran Anh Q.
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