Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Patent
1998-04-30
2000-07-18
Ellis, Richard L.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
712226, 712228, 712205, 712208, 712244, G06F 930, G06F 9312, G06F 948
Patent
active
060921854
ABSTRACT:
A computer processor which has an apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer provides a method for alleviating design deficiencies in the processor. The E-unit further contains a mechanism for transmitting the opcode and a desired action back to the Instruction Unit (I-unit) where it may be compared with the next instruction that is decoded. Furthermore, the E-unit opcode compare logic contains a mechanism for breaking infinite loops that may result. This E-unit opcode compare mechanism, may also be used for other purposes such as detecting invalid opcodes and other exception checking since it may allow for a faster cycle time of the processor than if this logic were implemented in the I-unit.
REFERENCES:
patent: 4651321 (1987-03-01), Woffinden et al.
patent: 5790843 (1998-08-01), Borkenhagen et al.
patent: 5870598 (1999-02-01), White et al.
"Opcode Compare Facility" Research Disclosure, Jul. 1990, No. 315, PO889-0224.
"Designing Flexibility into Hardwired Logic" IBM Technical Disclosure Bulletin, vol. 37, No. 3, Mar. 1994, pp. 321-324.
Check Mark Anthony
Slegel Timothy John
Augspurger Lynn L.
Chang Jung-won
Ellis Richard L.
International Business Machines - Corporation
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