ONO flash memory array for improving a disturbance between...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S411000, C438S286000

Reexamination Certificate

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06917073

ABSTRACT:
To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

REFERENCES:
patent: 5032881 (1991-07-01), Sardo et al.
patent: 6664588 (2003-12-01), Eitan
patent: 2003/0160280 (2003-08-01), Yoshino

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