ONO dielectric for memory cells

Details ONO dielectric for memory cells ONO dielectric for memory cells

2003-04-16

2004-11-23

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000

Reexamination Certificate

active

06822284

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to semiconductor devices and fabrication methods and, more particularly, to an ONO dielectric for flash memory cells and method for fabricating the same.
BACKGROUND
A semiconductor memory product generally includes a memory array that comprises a matrix of memory cells. One type of semiconductor device is a flash memory device, which includes flash memory cells. Each flash memory cell includes a floating-gate electrode for storing electrical charge. The electrical charge is provided from a channel region underneath the floating-gate electrode. The floating-gate electrode typically includes a dielectric material for storing the electrical charge. A common dielectric structure for a floating-gate electrode is an oxide-nitride-oxide (“ONO”) structure.
This type of structure plays a role in determining operating characteristics and reliability of the flash memory device. For example, a high quality ONO dielectric structure should provide, e.g., low defect density, long mean time to failure, and high charge retention capability.
One method for forming an ONO dielectric uses a single wafer thermal process. However, because of short reaction time, this process produces an ONO dielectric material with an undesirably low density structure. Due to the low density of the structure, the ONO material may be encroached during the subsequent manufacturing process, resulting in a decreased gate coupling ratio (“GCR”) and low yields.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a method of fabricating a semiconductor device that includes providing a wafer substrate, forming a first oxide layer over the wafer substrate using a single wafer low pressure chemical vapor deposition oxidation process, forming a second oxide layer over the first oxide layer by a single wafer oxidation process, forming a nitride layer over the second oxide layer using a low temperature and pressure deposition process, and growing a top oxide layer over the nitride layer.
Also in accordance with the invention, there is provided a method of manufacturing a semiconductor device that includes providing a wafer substrate, forming a first oxide layer over the wafer substrate using a single wafer low pressure chemical vapor deposition oxidation process, first oxide layer having a first etch rate, forming a second oxide layer over the first oxide layer by a single wafer oxidation process, second oxide layer having a second etch rate, forming a nitride layer over the second oxide layer, the second oxide layer having a third etch rate, and growing a top oxide layer over the nitride layer, wherein the third etch rate is greater than the first etch rate and the second etch rate.
Further in accordance with the present invention, there is provided a semiconductor device that includes a substrate, and a floating-gate electrode formed over the substrate. The floating-gate electrode includes a first oxide layer formed over the substrate, a second oxide layer formed over the first oxide layer, a nitride layer formed over the second oxide layer, and a top oxide layer formed over the nitride layer, wherein the first oxide layer is formed using a single wafer low pressure chemical vapor deposition oxidation process, the second oxide layer is formed by a single wafer oxidation process, and the nitride layer is formed using a low temperature and pressure deposition process.
Additional features and advantages consistent with the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages consistent with the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 6265268 (2001-07-01), Halliyal et al.
patent: 2002/0117709 (2002-08-01), Weimer et al.
patent: 2003/0148629 (2003-08-01), Ohmi et al.

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