Static information storage and retrieval – Floating gate
Reexamination Certificate
2004-08-31
2008-10-21
Le, Vu A (Department: 2824)
Static information storage and retrieval
Floating gate
C365S185180
Reexamination Certificate
active
07440317
ABSTRACT:
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.
REFERENCES:
patent: 3858060 (1974-12-01), Kenyon
patent: 3918033 (1975-11-01), Case et al.
patent: 3964085 (1976-06-01), Kahng et al.
patent: 3978577 (1976-09-01), Bhattacharyya et al.
patent: 4488262 (1984-12-01), Basire et al.
patent: 4754310 (1988-06-01), Coe
patent: 4791604 (1988-12-01), Lienau et al.
patent: 4829482 (1989-05-01), Owen
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5043946 (1991-08-01), Yamauchi et al.
patent: 5382814 (1995-01-01), Ashley et al.
patent: 5396454 (1995-03-01), Nowak
patent: 5488243 (1996-01-01), Tsuruta et al.
patent: 5557569 (1996-09-01), Smayling et al.
patent: 5621683 (1997-04-01), Young
patent: 5627779 (1997-05-01), Odake et al.
patent: 5686739 (1997-11-01), Baba
patent: 5801993 (1998-09-01), Choi
patent: 5814853 (1998-09-01), Chen
patent: 5963476 (1999-10-01), Hung et al.
patent: 5981335 (1999-11-01), Chi
patent: 6104045 (2000-08-01), Forbes et al.
patent: 6201734 (2001-03-01), Sansbury et al.
patent: 6243296 (2001-06-01), Sansbury
patent: 6248626 (2001-06-01), Kumar et al.
patent: 6294427 (2001-09-01), Furuhata et al.
patent: 6366501 (2002-04-01), Thurgate et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6545297 (2003-04-01), Noble et al.
patent: 6574143 (2003-06-01), Nakazato
patent: 6600188 (2003-07-01), Jiang et al.
patent: 6611452 (2003-08-01), Han
patent: 6617651 (2003-09-01), Ohsawa
patent: 6638627 (2003-10-01), Potter
patent: 6653174 (2003-11-01), Cho et al.
patent: 6653175 (2003-11-01), Nemati et al.
patent: 6660616 (2003-12-01), Babcock et al.
patent: 6661042 (2003-12-01), Hsu
patent: 6674120 (2004-01-01), Fujiwara
patent: 6812504 (2004-11-01), Bhattacharyya
patent: 6845034 (2005-01-01), Bhattacharyya
patent: 6881994 (2005-04-01), Lee et al.
patent: 6888200 (2005-05-01), Bhattacharyya
patent: 6903969 (2005-06-01), Bhattacharyya
patent: 6917078 (2005-07-01), Bhattacharyya
patent: 6965129 (2005-11-01), Horch et al.
patent: 7042027 (2006-05-01), Bhattacharyya
patent: 7245535 (2007-07-01), McCollum et al.
patent: 7291519 (2007-11-01), Bhattacharyya
patent: 7339830 (2008-03-01), Bhattacharyya
patent: 2002/0048190 (2002-04-01), King
patent: 2002/0105023 (2002-08-01), Kuo et al.
patent: 2003/0042534 (2003-03-01), Bhattacharyya et al.
patent: 2003/0072126 (2003-04-01), Bhattachrayya
patent: 2003/0089942 (2003-05-01), Bhattacharyya
patent: 2003/0151948 (2003-08-01), Bhattacharyya et al.
patent: 2003/0160277 (2003-08-01), Bhattacharyya et al.
patent: 2004/0007734 (2004-01-01), Kato et al.
patent: 2004/0014304 (2004-01-01), Bhattacharyya
patent: 2004/0041206 (2004-03-01), Bhattacharyya
patent: 2005/0001232 (2005-01-01), Bhattacharyya
patent: 2005/0025353 (2005-02-01), Bhattacharya
patent: 2005/0250261 (2005-11-01), Bhattacharyya
patent: 2005/0263763 (2005-12-01), Bhattacharyya
patent: 2005/0269628 (2005-12-01), King
patent: 2005/0280023 (2005-12-01), Bhattacharyya
patent: 2006/0043411 (2006-03-01), Bhattacharayya
patent: 2006/0227601 (2006-10-01), Bhattacharyya
patent: 61-166078 (1986-07-01), None
Bauer, F , et al., “Design aspects of MOS controlled thyristor elements”,International Electron Devices Meeting 1989. Technical Digest, (1989),297-300.
Bhattacharyya, A. , “Physical & Electrical Characteristics of LPCVD Silicon Rich Nitride”,ECS Technical Digest, J. Eletrochem. Soc., 131(11), 691 RDP, New Orleans,(1984),469C.
Carter, R J., “Electrical Characterization of High-k Materials Prepared By Atomic Layer CVD”,IWGI, (2001),94-99.
Chang, H R., et al., “MOS trench gate field-controlled thyristor”,Technical Digest—International Electron Devices Meeting, (1989),293-296.
Choi, J D., et al., “A0.15 um NAND Flash Technology with ).11 um2 cell Size for 1 Gbit Flash Memory”,IEDM Technical Digest, (2000),767-770.
Fazan, P , et al., “Capacitor-Less 1-Transistor DRAM”,IEEE International SOI Conference, (2002),10-13.
Frohman-Bentchkowsky, D , “An integrated metal-nitride-oxide-silicon (MNOS) memory”,Proceedings of the IEEE, 57(6), (Jun. 1969),1190-1192.
Han, Kwangseok , “Characteristics of P-Channel Si Nano-Crystal Memory”,IEDM Technical Digest, International Electron Devices Meeting, (Dec. 10-13, 2000),309-312.
Jagar, S , “Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization”,International Electron Devices Meeting 1999. Technical Digest, (1999),293-6.
Kumar, M. J., “Lateral Schottky Rectifiers for Power Integrated Circuits”,International Workshop on the Physics of Semiconductor Devices, 11th, 4746, Allied Publishers Ltd., New Delhi, India,(2002),414-421.
Lai, S K., et al., “Comparison and trends in Today's dominant E2 Technologies”,IEDM Technical Digest, (1986),580-583.
Nemati, F , et al., “A novel high density, low voltage SRAM cell with a vertical NDR device”,1998 Symposium on VLSI Technology Digest of Technocal Papers, (1998),66-7.
Nemati, F , et al., “A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories”,International Electron Devices Meeting 1999. Technical Digest, (1999),283-6.
Ohsawa, T , “Memory design using one-transistor gain cell on SOI”,IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 1, (2002),152-455.
Okhonin, S , “A SOI capacitor-less 1T-DRAM concept”,2001 IEEE International SOI Conference. Proceedings, IEEE. 2001, (2000),153-4.
Shinohe, T , et al., “Ultra-high di/dt 2500 V MOS assisted gate-triggered thyristors (MAGTs) for high repetition excimer laser system”,International Electron Devices Meeting 1989. Technical Digest, (1989),301-4.
Sze, S. M., “Table 3: Measured Schottky Barrier Heights”,In: Physics of Semiconductor Devices, John Wiley & Sons, Inc.,(1981),p. 291.
Tiwari, Sandip , “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage”,Int'l Electron Devices Meeting: Technical Digest, Washington, DC,(Dec. 1995),521-524.
Van Meer, H , “Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications”,2001 IEEE International SOI Conference, (2001),45-6.
Zhang, H. , “Atomic Layer Deposition of High Dielectric Constant Nanolaminates”,Journal of The Electrochemical Society, 148(4), (Apr. 2001),F63-F66.
U.S. Appl. No. 10/232,846 Non final office action mailed Oct. 1, 2004, 9 pgs.
U.S. Appl. No. 10/232,846 Response filed Jan. 3, 2005 to Non final office action mailed Oct. 1, 2004, 17 pgs.
U.S. Appl. No. 10/425,483 Non final office action mailed Mar. 29, 2004, 7 pgs.
U.S. Appl. No. 10/425,483 Response filed Jun. 22, 2004 to Non final office action mailed Mar. 29, 2004, 7 pgs.
U.S. Appl. No. 10/930,440 Non final office action mailed Mar. 21, 2006, 11 pgs.
U.S. Appl. No. 10/930,440 Response filed Jun. 21, 2006 to Non final office action mailed Mar. 21, 2006, 12 pgs.
U.S. Appl. No. 11/158,744, Non-Final Office Action mailed Aug. 6, 2007, 18 pgs.
U.S. Appl. No. 11/656,602 Non final office action mailed May 16, 2007, 19 pgs.
U.S. Appl. No. 11/656,602 Response filed Aug.
Le Vu A
Micro)n Technology, Inc.
Schwegman Lundberg & Woessner, P.A.
LandOfFree
One transistor SOI non-volatile random access memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with One transistor SOI non-volatile random access memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and One transistor SOI non-volatile random access memory cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4001173