One transistor SOI non-volatile random access memory cell

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S349000, C257S351000

Reexamination Certificate

active

06888200

ABSTRACT:
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

REFERENCES:
patent: 3918033 (1975-11-01), Case et al.
patent: 3964085 (1976-06-01), Kahng et al.
patent: 3978577 (1976-09-01), Bhattacharyya et al.
patent: 4488262 (1984-12-01), Basire et al.
patent: 4791604 (1988-12-01), Lienau et al.
patent: 4829482 (1989-05-01), Owen
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5043946 (1991-08-01), Yamauchi et al.
patent: 5396454 (1995-03-01), Nowak
patent: 5488243 (1996-01-01), Tsuruta et al.
patent: 5557569 (1996-09-01), Smayling et al.
patent: 5621683 (1997-04-01), Young
patent: 5627779 (1997-05-01), Odake et al.
patent: 5801993 (1998-09-01), Choi
patent: 5814853 (1998-09-01), Chen
patent: 5963476 (1999-10-01), Hung et al.
patent: 5981335 (1999-11-01), Chi
patent: 6104045 (2000-08-01), Forbes et al.
patent: 6201734 (2001-03-01), Sansbury et al.
patent: 6243296 (2001-06-01), Sansbury
patent: 6248626 (2001-06-01), Kumar et al.
patent: 6294427 (2001-09-01), Furuhata et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6545297 (2003-04-01), Noble, Jr. et al.
patent: 6574143 (2003-06-01), Nakazato
patent: 6600188 (2003-07-01), Jiang et al.
patent: 6611452 (2003-08-01), Han
patent: 6638627 (2003-10-01), Potter
patent: 6653174 (2003-11-01), Cho et al.
patent: 6653175 (2003-11-01), Nemati et al.
patent: 6660616 (2003-12-01), Babcock et al.
patent: 20020048190 (2002-04-01), King
patent: 20020105023 (2002-08-01), Kuo et al.
patent: 20030042534 (2003-03-01), Bhattacharyya et al.
patent: 20030072126 (2003-04-01), Bhattacharyya
patent: 20030089942 (2003-05-01), Bhattacharyya
patent: 20030151948 (2003-08-01), Bhattacharyya et al.
patent: 20030160277 (2003-08-01), Bhattacharyya et al.
patent: 20040007734 (2004-01-01), Kato et al.
patent: 20040014304 (2004-01-01), Bhattacharyya
patent: 61-166078 (1986-07-01), None
Bhattacharyya, A. , “Physical & Electrical Characteristics of LPCVD Silicon Rich Nitride”,ECS Technical Digest, J. Electrochem. Soc., 131(11), 691 RDP, New Orleans,(1984),469C.
Frohman-Bentchkowsky, D , et al., “An integrated metal-nitride-oxide-silicon (MNOS) memory”,Proceedings of the IEEE, 57(6), (Jun. 1969),1190-1192.
Ohsawa, T , “Memory design using on-transistor gain cell on SOI”,IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 1, (2002),152-455.
Okhonin, S , “A SOI capacitor-less 1T-DRAM concept”,2001 IEEE International SOI Conference. Proceedings, IEEE. 2001, (2000),153-4.
Bauer, F , et al., “Design aspects of MOS controlled thyristor elements”,International Electron Devices Meeting 1989. Technical Digest, (1989),297-300.
Chang, H R., et al., “MOS trench gate field-controlled thyristor”,Technical Digest—International Electron Devices Meeting, (1989),293-296.
Fazan, P , et al., “Capacitor-Less 1-Transistor DRAM”,IEEE International SOI Conference, (2002),10-13.
Jagar, S , “Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization”,International Electron Devices Meeting 1999. Technical Digest, (1999),293-6.
Nemati, F , et al., “A novel high density, low voltage SRAM cell with a vertical NDR device”,1998 Symposium on VLSI Technology Digest of Technical Papers, (1998),66-7.
Nemati, F , et al., “A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories”,International Electron Devices Meeting 1999. Technical Digest, (1999),283-6.
Shinohe, T , et al., “Ultra-high di/dt 2500 V MOS assisted gate-triggered thyristors (MAGTs) for high repetition excimer laser system”,International Electron Devices Meeting 1989. Technical Digest, (1989),301-4.
Van Meer, H , “Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications”,2001 IEEE International SOI Conference, (2001),45-6.
Carter, RJ., “Electrical Characterization of High-k Materials Prepared By Atomic Layer CVD”, IWGI, (2001), 94-99.*
Choi, J D., et al., “A0.15 um NAND Flash Technology with .11 m2 cell Size for 1 Gbit Flash Memory”,IEDM Technical Digest, (2000), 767-770.*
Han, Kwangseok, “Characteristics of P-Channel Si Nano-Crystal Memory”,IEDM Technical Digest, International Electron Devices Meeting, (Dec. 10-13, 2000), 309-312.*
Kumar, M. J., “Lateral Schottky Rectifiers for Power Integrated Circuits”,International Workshop on the Physics of Semiconductor Devices, 11th, 4746, Allied Publishers Ltd., New Delhi, India, (2002), 414-421.*
Lai, S K., et al., “Comparison and treats in Today's dominant E2 Technologies”,IEDM Technical Digest, (1986), 580-583.*
SZE, S. M., “Table 3: Measured Schottky Barrier Heights”,In: Physics of Semiconductor Devices, John Wiley & Sons, Inc., (1981), p. 291.*
Tiwari, Sandip , “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage”,Int'l Electron Devices Meeting; Technical Digest,Washington, DC, (Dec. 1995) 521-524.*
Zhang, H., “Atomic Layer Deposition of High Dielectric Constant Nanolaminates”,Journal of The Electrochemical Society, 148(4), (Apr. 2001), F63-F66.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

One transistor SOI non-volatile random access memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with One transistor SOI non-volatile random access memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and One transistor SOI non-volatile random access memory cell will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3397569

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.