One transistor-one capacitor memory cell

Details One transistor-one capacitor memory cell One transistor-one capacitor memory cell

1978-08-28

1983-07-05

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

357 23, G11C 1124

Patent

active

043922104

ABSTRACT:
An integrated circuit memory cell pair having its data lines insulatively disposed from the semiconductor substrate at all points other than the point of electrical contact to the transistors of each memory cell. The semiconductor substrate has drain and source regions about the transmission channel of the field effect transistor and has a first capacitor electrode integral with one terminal of the transistor. A first polysilicon layer insulatively disposed from the substrate provides a conductive layer for a second capacitor electrode for each memory cell. A second insulatively disposed polysilicon layer provides the gate regions of the transistors and the data lines. The data lines make electrical contact through a self-aligned buried contact. Using this construction, a highly dense memory cell array is achieved without sacrificing capacitor area.

REFERENCES:
patent: 4012757 (1977-03-01), Koo
patent: 4164751 (1979-08-01), Tasch
patent: 4168538 (1979-09-01), Meusburger
Kuo et al., 16-K RAM Built with Proven Process May Offer High Start-Up Reliability, Electronics, 5/13/76, pp. 81-86.
Lee et al., Merged Charge Memory (MCM), A New Random Access Cell, International Electron Devices Meeting, 1976, Washington, D.C., pp. 5-20.
Boll et al., Design of a High-Performance M24-b Switched Capacitor, p-Channel IGFET Memory Chip, IEEE J. of Solid-State Cir., vol. 8, No. 5, 10/73, pp. 310-318.
Barson et al., High-Density Single-Device Memory Cell, IBM Tech. Disc. Bull., vol. 16, No. 6, 11/73, p. 1698.

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