One transistor flash memory cell

Details One transistor flash memory cell One transistor flash memory cell

2005-06-21

2005-06-21

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S318000

Reexamination Certificate

active

06909139

ABSTRACT:
An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line13substantially vertically aligned with a buried source bit line14. The memory array separates the columns with deep trenches46that may also be formed into charge pump capacitors.

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patent: WO 02/15190 (2002-02-01), None
Chi-Nan Brian Li et al., “A Novel Uniform-Channel-Program-Erase (UCPE) Flash EEPROM Using an Isolated P-well Structure”, IEEE, 2000 (Apr. 2000) 0-7803-6441-4/00.
Evans Ching-Song Yang, et al., “Novel Bi-Directional Tunneling Program/Erase NOR(BiNOR)-Type Flash EEPROM”, IEEE 1999, 0018-9383/99, Voil 46, No. 6, Jun. 1999, pp. 1294-1296.

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