One transistor cell flash memory assay with over-erase protectio

Details One transistor cell flash memory assay with over-erase protectio One transistor cell flash memory assay with over-erase protectio

1991-05-03

1993-08-31

Zazworsky, John

Static information storage and retrieval

Read/write circuit

Erase

365185, 365186, 365900, G11C 1140, G11C 1600

Patent

active

052415074

ABSTRACT:
A memory array formed from single transistor flash cells employs prevention circuitry for minimizing the effect of any floating gates in an over-erased state when accessing data stored in the memory array device. The prevention circuit includes a column line coupling a current limiting device in each row together in a common column. The memory array device also employs a row current limiting device which couples that row of flash cells to the erase potential. The second row switching means is activated to prevent a false signal generated by an over-erased flash cell in the same column as a selected flash cell being accessed for data from masking the data retrieval from the desired flash cell.

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Lahti et al., "Store Data in a Flash," Byte magazine, pp. 311-318, Nov. 1990.

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